CP3BT23 Datasheet, PDF (41/260 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

8.5.16 Flash Memory Recovery Time Reload Register 8.5.18 Flash Memory Auto-Read Register 1 (FMAR1/
(FMRCV/FSMRCV)
FSMAR1)
The FMRCV/FSMRCV register is a byte-wide read/write
register that controls the recovery delay time between two
flash memory accesses. Software must not modify this reg-
ister while a program/erase operation is in progress (FM-
BUSY set). At reset, this register is initialized to 04h if the
flash memory is idle. The CPU bus master has read/write
access to this register.
The FMAR1 register contains a copy of the Protection Word
from Information Block 1. The Protection Word is sampled
at reset. The contents of the FMAR1 register define the cur-
rent Flash memory protection settings. The CPU bus mas-
ter has read-only access to this register. The FSMAR1
register has the same value as the FMAR1 register. The for-
mat is the same as the format of the Protection Word (see
Section 8.4.2).
7
0
FTRCV
15 13 12 10 9 7 6 4 3 1 0
WRPROT RDPROT ISPE EMPTY BOOTAREA 1
FTRCV
The Flash Timing Recovery Delay Count field
specifies a delay of (FTRCV + 1) prescaler 8.5.19 Flash Memory Auto-Read Register 2 (FMAR2/
output clocks.
FSMAR2)
8.5.17 Flash Memory Auto-Read Register 0 (FMAR0/
FSMAR0)
The FMAR0/FSMAR0 register contains a copy of the Func-
te ^{tion Word from Information Block 0. The Function Word is}
sampled at reset. The CPU bus master has read-only ac-
cess to this register. The FSMAR0 register has the same
value as the FMAR0 register
The FMAR2 register is a word-wide read-only register,
which is loaded during reset. It is used to build the Code
Area start address. At reset, the CPU executes a branch,
using the contents of the FMAR2 register as displacement.
The CPU bus master has read-only access to this register.
The FSMAR2 register has the same value as the FMAR2
register.
15
0
7
0
le ^Reserved
CADR7:0
15
14
11
CADR15
CADR14:11
10
8
CADR10:8
oCADR10:0 The Code Area Start Address (bits 10:0) con-
tains the lower 11 bits of the Code Area start
address. The CADR10:0 field has a fixed val-
s ueof0.
CADR14:11 The Code Area Start Address (bits 14:11) are
loaded during reset with the inverted value of
BOOTAREA3:0.
b CADR15 The Code Area Start Address (bits 15) con-
tains the upper bit of the Code Area start ad-
dress. The CADR15 field has a fixed value of
O ^0.
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