CP3BT23 Datasheet, PDF (48/260 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

10.0 Interrupts
The Interrupt Control Unit (ICU) receives interrupt requests 10.2.1 Maskable Interrupt Processing
from internal and external sources and generates interrupts
to the CPU. Interrupts from the timers, UARTs, Microwire/
SPI interface, and Multi-Input Wake-Up module are all
maskable interrupts. The highest-priority interrupt is the
Non-Maskable Interrupt (NMI), which is triggered by a falling
edge received on the NMI input pin.
Interrupt vector numbers are always positive, in the range
10h to 3Fh. The IVCT register contains the interrupt vector
of the enabled and pending interrupt with the highest priori-
ty. The interrupt vector 10h corresponds to IRQ0 and the
lowest priority, while the vector 3Fh corresponds to IRQ47
and the highest priority. The CPU performs an interrupt ac-
The priorities of the maskable interrupts are hardwired and knowledge bus cycle on receiving a maskable interrupt re-
therefore fixed. The implemented interrupts are named quest from the ICU. During the interrupt acknowledge cycle,
IRQ0 through IRQ47, in which IRQ0 has the lowest priority a byte is read from address FF FE00h (IVCT register). The
and IRQ47 has the highest priority. (IRQ0 is not implement- byte is used as an index into the Dispatch Table to deter-
ed, so IRQ1 is the lowest priority interrupt that normally may mine the address of the interrupt handler.
occur.)
Because IRQ0 is not connected to any interrupt source, it
10.1 NON-MASKABLE INTERRUPTS
The Interrupt Control Unit (ICU) receives the external NMI
input and generates the NMI signal driven to the CPU. The
NMI input is an asynchronous input with Schmitt trigger
characteristics and an internal synchronization circuit,
therefore no external synchronizing circuit is needed. The
te ^{NMI pin triggers an exception on its falling edge.}
would seem that the interrupt vector would never return the
value 10h. If it does return a value of 10h, the entry in the
dispatch table should point to a default interrupt handler that
handles this error condition. One possible condition for this
to occur is deassertion of the interrupt before the interrupt
acknowledge cycle.
10.3 INTERRUPT CONTROLLER REGISTERS
10.1.1 Non-Maskable Interrupt Processing
Table 19 lists the ICU registers.
The CPU performs an interrupt acknowledge bus cycle
when beginning to process a non-maskable interrupt.
At reset, NMI interrupts are disabled and must remain dis-
abled until software initializes the interrupt table, interrupt
le ^{base register (INTBASE), and the interrupt mode. The ex-}
ternal NMI interrupt is enabled by setting the EXNMI.EN-
LCK bit and will remain enabled until a reset occurs.
Alternatively, the external NMI interrupt can be enabled by
setting the EXNMI.EN bit and will remain enabled until an in-
terrupt event or a reset occurs.
o _{10.2 MASKABLE INTERRUPTS}
The ICU receives level-triggered interrupt request signals
s ^{from 47 sources and generates a vectored interrupt to the}
CPU when required. Priority among the implemented inter-
rupt sources (named IRQ1 through IRQ47) is fixed.
The maskable interrupts are globally enabled and disabled
b ^{by the E bit in the PSR register. The EI and DI instructions}
are used to set (enable) and clear (disable) this bit. The glo-
bal maskable interrupt enable bit (I bit in the PSR) must also
be set before any maskable interrupts are taken.
Each interrupt source can be individually enabled or dis-
O ^{abled under software control through the ICU interrupt en-}
Table 19 Interrupt Controller Registers
Name
IVCT
NMISTAT
EXNMI
ISTAT0
ISTAT1
ISTAT2
IENAM0
Address
FF FE00h
FF FE02h
FF FE04h
FF FE0Ah
FF FE0Ch
FF FE20h
FF FE0Eh
Description
Interrupt Vector
Register
Non-Maskable
Interrupt Status
Register
External NMI Trap
Control and Status
Register
Interrupt Status
Register 0
Interrupt Status
Register 1
Interrupt Status
Register 2
Interrupt Enable and
Mask Register 0
able registers and also through interrupt enable bits in the
peripherals that request the interrupts. The ICU supports
IENAM1
FF FE10h
Interrupt Enable and
Mask Register 1
IRQ0, but in the CP3BT23 it is not connected to any inter-
rupt source.
IENAM2
FF FE22h
Interrupt Enable and
Mask Register 2
47
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