CP3BT23 Datasheet, PDF (112/260 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

18.10 CAN CONTROLLER REGISTERS
Table 44 lists the CAN registers.
Table 44 CAN Controller Registers
Name
Address
Description
Table 44 CAN Controller Registers
Name
CIEN1
Address
0E F30Ch
Description
CAN Interrupt
Enable Register 1
CNSTAT
See
Table 43
CAN Buffer Status/
Control Register
CIPND1
0E F30Eh
CAN Interrupt
Pending Register 1
CGCR0
CTIM0
GMSKX0
GMSKB0
BMSKX0
BMSKB0
CIEN0
CIPND0
CICLR0
CICEN0
CSTPND0
CANEC0
CEDIAG0
CTMR0
CGCR1
CTIM1
0E F100h
CAN Global
Configuration
CICLR1
0E F310h
CAN Interrupt
Clear Register 1
0E F102h
0E F104h
0E F106h
0E F108h
te ^{0E F10Ah}
0E F10Ch
le ^{0E F10Eh}
0E F110h
o ^{0E F112h}
0E F114h
s _{0E F116h}
0E F118h
b_{0E F11Ah}
O^{0E F300h}
Register 0
CAN Timing
Register 0
Global Mask
Register 0
Global Mask
Register 0
Basic Mask
Register 0
Basic Mask
Register 0
CAN Interrupt
Enable Register 0
CAN Interrupt
Pending Register 0
CAN Interrupt
Clear Register 0
CAN Interrupt Code
Enable Register 0
CAN Status
Pending Register 0
CAN Error
Counter Register 0
CAN Error
Diagnostic Register 0
CAN Timer Register 0
CAN Global
Configuration
Register 1
CICEN1
CSTPND1
CANEC1
CEDIAG1
CTMR1
0E F312h
CAN Interrupt Code
Enable Register 1
0E F314h
CAN Status
Pending Register 1
0E F316h
CAN Error
Counter Register 1
0E F318h
CAN Error
Diagnostic Register 1
0E F31Ah CAN Timer Register 1
18.10.1 Buffer Status/Control Register (CNSTAT)
The buffer status (ST), the buffer priority (PRI), and the data
length code (DLC) are controlled by manipulating the con-
tents of the Buffer Status/Control Register (CNSTAT). The
CPU and CAN module have access to this register.
15
12 11
87
43
0
DLC
Reserved
PRI
ST
0
R/W
ST
The Buffer Status field contains the status in-
formation of the buffer as shown in Table 45.
This field can be modified by the CAN module.
The ST0 bits acts as a buffer busy indication.
When the BUSY bit is set, any write access to
the buffer is disabled with the exception of the
lower byte of the CNSTAT register. The CAN
module sets this bit if the buffer data is cur-
rently copied from the hidden buffer or if a
message is scheduled for transmission or is
currently transmitting. The CAN module al-
0E F302h
CAN Timing
Register 1
ways clears this bit on a status update.
GMSKX1
0E F304h
Global Mask
Register 1
GMSKB1
0E F306h
Global Mask
Register 1
BMSKX1
0E F308h Basic Mask Register 1
BMSKB1
0E F30Ah Basic Mask Register 1
111
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