CP3BT23 Datasheet, PDF (124/260 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

DRIVE
The Drive bit shows the output value on the
CANTX pin at the time of the error. Note that
a receiver will not drive the bus except during
ACK and during an active error flag.
18.10.17 CAN Timer Register (CTMRn)
18.11.1 External Connection
The CAN module uses the CANnTX and CANnRX pins to
connect to the physical layer of the CAN interface. They pro-
vide the functionality described in Table 57.
Table 57 External CAN Pins
The CTMRn register reports the current value of the Time
Stamp Counter as described in Section 18.8.
Signal Name
Type
Description
15
CTMR15:0
0
R
CANnTX Output Transmit data to the CAN bus
0
CANnRX Input Receive data from the CAN bus
The logic levels are configurable by the CTX and CRX bits
of the Global Configuration Register CGCRn (see “CAN
Global Configuration Register (CGCRn)” on page 116).
18.11.2 Transceiver Connection
The CTMRn register is a free running 16-bit counter. It con-
tains the number of CAN bits recognized by the CAN mod-
ule since the register has been cleared. The counter starts
to increment from the value 0000b after a hardware reset. If
the Timer Stamp Enable bit (TSTPEN) in the CGCRn regis-
ter is set, the counter will also be cleared on a message
te ^{transfer of the message buffer 0.}
An external transceiver chip must be connected between
the CAN block and the bus. It establishes a bus connection
in differential mode and provides the driver and protection
requirements. Figure 62 shows a possible ISO-High-Speed
configuration.
120 Termination
The contents of CTMR are captured into the Time Stamp
register of the message buffer after successfully sending or
receiving a frame, as described in “Time Stamp Counter” on
page 109.
18.11 SYSTEM START-UP AND MULTI-INPUT
le ^WAKE-UP
After system start-up, all CAN-related registers are in their
reset state. The CAN module can be enabled after all con-
figuration registers are set to their desired value. The follow-
ing initial settings must be made:
o ! Configure the CAN Timing register (CTIM). See “Bit
Time Logic” on page 100.
! Configure every buffer to its function as receive/transmit.
See “Buffer Status/Control Register (CNSTAT)” on
s _{page 111.}
! Set the acceptance filtering masks. See “Acceptance Fil-
tering” on page 102.
! Enable the CAN interface. See “CAN Global Configura-
b _{tion Register (CGCRn)” on page 116.}
CPU Bus
CR16CAN
CANnRX
CANnTX
Transceiver Chip
VCC
5 _REF
4 _RX
1
TX
3
VCC
7
BUS_H
6
BUS_L
RS
GND
8
2
CAN bus
signals
To other
modules
120
Figure 62. External Transceiver
DS282
Before disabling the CAN module, software must make sure
that no transmission is still pending.
Note: Activity on the CAN bus can wake up the device from
O ^{a reduced-power mode by selecting the CANnRX pin as an}
18.11.3 Timing Requirements
Processing messages and updating message buffers re-
quire a certain number of clock cycles, as shown in
Table 58. These requirements may lead to some restrictions
input to the Multi-Input Wake-Up module. In this case, the _{regarding the Bit Time Logic settings and the overall CAN}
CAN module must not be disabled before entering the re- _{performance which are described below in more detail. Wait}
duced-power mode. Disabling the CAN module also dis- _{cycles need to be added to the cycle count for CPU access}
ables the CANnRX pin. As an alternative, the CANnRX pin _{to the object memory as described in CPU Access to CAN}
can be connected to any other input pin of the Multi-Input _{Registers/Memory on page 110. The number of occurrenc-}
Wake-Up module. This input channel must then be config- _{es per frame is dependent on the number of matching iden-}
ured to trigger a wake-up event on a falling edge (if a domi- _tifiers.
nant bit is represented by a low level). In this case, the CAN
module can be disabled before entering the reduced-power
mode. After waking up, software must enable the CAN mod-
ule again. All configuration and buffer registers still contain
the same data they held before the reduced-power mode
was entered.
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