CP3BT23 Datasheet, PDF (55/260 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

11.5 SYSTEM CLOCK
The System Clock drives most of the on-chip modules, in-
cluding the CPU. Typically, it is driven by the Main Clock, but
it can also be driven by the PLL. In either case, the clock sig-
nal is passed through a programmable divider (scale factors
from ÷1 to ÷16).
11.6 AUXILIARY CLOCKS
The external reset circuits presented in the following sec-
tions provide varying levels of additional fault tolerance and
expandability and are presented as possible examples of
solutions to be used with the CP3BT23. It is important to
note, however, that any design for the reset circuit and pow-
er supply must meet the timing requirements shown in
Figure 7.
Auxiliary Clock 1 and Auxiliary Clock 2 are generated from
2.25V
IOVCC
Main Clock for use by certain peripherals. Auxiliary Clock 1
is available for the Bluetooth controller and the Advanced
Audio Interface. Auxiliary Clock 2 is available for the CVSD/
2.25V
Core VCC
PCM transcoder and the 12-bit ADC. The Auxiliary clocks
may be configured to keep these peripherals running when
the System Clock is slowed down or suspended during low-
power modes.
RESET
11.7 POWER-ON RESET
The CP3BT23 has specific Power On Reset (POR) timing
requirements that must be met to prevent corruption of the
on-chip flash program and data memories. This timing se-
quence shown in Figure 7.
Main
Clock
Power Up
Power Down
DS515
te ^{All reset circuits must ensure that this timing sequence is al-}
ways maintained during power-up and power-down. The
design of the power supply also affects how this sequence
is implemented.
The power-up sequence is:
le 1. The RESET pin must be held low until both IOVCC and
VCC have reached the minimum levels specified in the
DC Characteristics section. IOVCC and VCC are al-
lowed to reach their nominal levels at the same time
which is the best-case scenario.
2. After both of these supply voltage rails have met this
o ^{condition, then the RESET pin may be driven high. At}
power-up an internal 14-bit counter is set to 3FFFh and
begins counting down to 0 after the crystal oscillator
becomes stable. When this counter reaches 0, the on-
s ^{chip RESET signal is driven high unless the external}
RESET pin is still being held low. This prevents the
CP3BT23 from coming out of reset with an unstable
clock source.
b ^{The power-down sequence is:}
Figure 7. Power-On Reset Timing
11.8 EXTERNAL RESET
External reset is triggered by assertion of the RESET input.
As with power-on reset, the on-chip 14-bit counter enforces
a minimum reset cycle time.
11.8.1 Simple External Reset
A simple external reset circuit with brown-out and glitch pro-
tection based on the LM809 3-Pin Microprocessor Reset
Circuit is shown in Figure 8. The LM809 produces a 240-ms
logic low reset pulse when the power supply rises above a
threshold voltage. Various reset thresholds are available for
the LM809, however the options for 2.93V and 3.08V are
most suitable for a CP3BT23 device operating from an IO-
VCC at 3.0V to 3.3V.
IOVCC
IOVCC
1. The RESET pin must be driven low as soon as either
the IOVCC or VCC voltage rail reaches the minimum
levels specified in the DC Characteristics.
2. The RESET pin must then be held low until the Main
O ^{Clock is stopped. The Main Clock will decay with the}
LM809
3-Pin Reset
Circuit
CP3BT2x
RESET
same profile as IOVCC.
GND
Meeting the power-down reset conditions ensures that soft-
ware will not be executed at voltage levels that may cause
incorrect program execution or corruption of the flash mem-
ories. This situation must be avoided because the Main
Clock decays with the IOVCC supply rather than stopping
immediately when IOVCC falls below the minimum specified
level.
DS496
Figure 8. Simple External Reset
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