CP3BT23 Datasheet, PDF (155/260 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

UBKD
The Break Detect bit indicates when a line UCTS
The Clear To Send bit indicates the state on
break condition occurs. This condition is de-
the CTS input. This functionality is only avail-
tected if RXD remains low for at least ten bit
able for the UART0 module.
times after a missing stop bit has been detect-
0 – CTS input is high.
ed at the end of a frame. The hardware auto-
1 – CTS input is low.
matically clears the UBKD bit on reading the UEFCI
The Enable Flow Control Interrupt bit controls
UnSTAT register, but only if the break condi-
whether a flow control interrupt is generated
tion on RXD no longer exists. If reading the
when the UDCTS bit changes from clear to
UnSTAT register does not clear the UBKD bit
set. This functionality is only available for the
because the break is still actively driven on
UART0 module.
the line, the hardware clears the bit as soon as
0 – Flow control interrupt disabled.
the break condition no longer exists (when the
1 – Flow control interrupt enabled.
RXD input returns to a high level).
UETI
The Enable Transmitter Interrupt bit, when
0 – No break condition occurred.
set, enables generation of an interrupt when
1 – Break condition occurred.
the hardware sets the UTBE bit.
URB9
te ^UXMIP
The Received 9th Data Bit holds the ninth
data bit, when the UART is configured to op-
erate in the 9-bit data format.
The Transmit In Progress bit indicates when
the UART is transmitting. The hardware sets
this bit when the UART is transmitting data
and clears the bit at the end of the last frame
bit.
0 – UART is not transmitting.
1 – UART is transmitting.
21.3.8 UART Interrupt Control Register (UnICTRL)
The UnICTRL register is a byte-wide register that contains
the receive and transmit interrupt status bits (read-only bits)
le ^{and the interrupt enable bits (read/write bits). The register is}
initialized to 01h at reset. The register format is shown be-
low.
UERI
UEEI
0 – Transmit buffer empty interrupt disabled.
1 – Transmit buffer empty interrupt enabled.
The Enable Receiver Interrupt bit, when set,
enables generation of an interrupt when the
hardware sets the URBF bit.
0 – Receive buffer full interrupt disabled.
1 – Receive buffer full interrupt enabled.
The Enable Receive Error Interrupt bit, when
set, enables generation of an interrupt when
the hardware sets the UERR bit in the Un-
STAT register.
0 – Receive error interrupt disabled.
1 – Receive error interrupt enabled.
21.3.9 UART Oversample Rate Register (UnOVR)
The UnOVR register is a byte-wide, read/write register that
specifies the oversample rate. At reset, the UnOVR register
is cleared. The register format is shown below.
765
4
3
2
10
o ^{UEEI UERI UETI UEFCI UCTS UDCTS URBF UTBE}
7
4
3
0
Reserved
UOVSR
UTBE
Obs ^URBF
The Transmit Buffer Empty bit is set by hard-
ware when the UART transfers data from the
UnTBUF register to the transmit shift register
for transmission. It is automatically cleared by
the hardware on the next write to the UnTBUF
register.
0 – Transmit buffer is loaded.
1 – Transmit buffer is empty.
The Receive Buffer Full bit is set by hardware
when the UART has received a complete data
frame and has transferred the data from the
UOVSR
The Oversampling Rate field specifies the
oversampling rate, as given in the following ta-
ble.
UOVSR3:0
0000–0110
0111
1000
Oversampling Rate
16
7
8
receive shift register to the UnRBUF register.
It is automatically cleared by the hardware
1001
9
when the UnRBUF register is read.
0 – Receive buffer is empty.
1010
10
1 – Receive buffer is loaded.
1011
11
UDCTS
The Delta Clear To Send bit indicates whether
the CTS input has changed state since the
1100
12
CPU last read this register. This functionality
is only available for the UART0 module.
1101
13
0 – No change since last read.
1110
14
1 – State has changed since last read.
1111
15
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