CP3BT23 Datasheet, PDF (57/260 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

11.9 CLOCK AND RESET REGISTERS
ACE1
When the Auxiliary Clock Enable bit is set and
Table 23 lists the clock and reset registers.
Table 23 Clock and Reset Registers
a stable Main Clock is provided, the Auxiliary
Clock 1 prescaler is enabled and generates
the first Auxiliary Clock. When the ACE1 bit is
clear or the Main Clock is not stable, Auxiliary
Name
Address
Description
Clock 1 is stopped. Auxiliary Clock 1 is used
CRCTRL
FF FC40h
Clock and Reset
Control Register
as the clock input for the Bluetooth LLC and
the Advanced Audio Interface. After reset this
bit is clear.
PRSFC
FF FC42h
High Frequency Clock
Prescaler Register
0 – Auxiliary Clock 1 is stopped.
1 – Auxiliary Clock 1 is active if the Main
Clock is stable.
PRSSC
FF FC44h
Low Frequency Clock ACE2
Prescaler Register
When the Auxiliary Clock Enable 2 bit is set
and a stable Main Clock is provided, the Aux-
iliary Clock 2 prescaler is enabled and gener-
PRSAC
FF FC46h
Auxiliary Clock
Prescaler Register
11.9.1 Clock and Reset Control Register (CRCTRL)
The CRCTRL register is a byte-wide read/write register that
controls the clock selection and contains the power-on reset
status bit. At reset, the CRCTRL register is initialized as de-
te ^{scribed below:}
76 5
4
3
2
1
0
Reserved POR ACE2 ACE1 PLLPWD FCLK SCLK
POR
le ^SCLK
o _FCLK
Obs ^PLLPWD
The Slow Clock Select bit controls the clock
source used for the Slow Clock.
0 – Slow Clock driven by prescaled Main
Clock.
1 – Slow Clock driven by 32.768 kHz oscilla-
tor.
The Fast Clock Select bit selects between the
12 MHz Main Clock and the PLL as the source
used for the System Clock. After reset, the
Main Clock is selected. Attempting to switch to
the PLL while the PLLPWD bit is set (PLL is
turned off) is ignored. Attempting to switch to
the PLL also has no effect if the PLL output
clock has not stabilized.
0 – The System Clock prescaler is driven by
the output of the PLL.
1 – The System Clock prescaler is driven by
the 12-MHz Main Clock. This is the de-
fault after reset.
The PLL Power-Down bit controls whether the
ates Auxiliary Clock 2. When the ACE2 bit is
clear or the Main Clock is not stable, the Aux-
iliary Clock 2 is stopped. Auxiliary Clock 2 is
used as the clock input for the CVSD/PCM
transcoder and the A/D converter. After reset
this bit is clear.
0 – Auxiliary Clock 2 is stopped.
1 – Auxiliary Clock 2 is active if the Main
Clock is stable.
The Power-On-Reset bit is set when a power-
turn-on condition has been detected. This bit
can only be cleared by software, not set. Writ-
ing a 1 to this bit will be ignored, and the pre-
vious value of the bit will be unchanged.
0 – Software cleared this bit.
1 – Software has not cleared his bit since the
last reset.
PLL is active or powered down (Stop PLL sig-
nal asserted). When this bit is set, the on-chip
PLL stays powered-down. Otherwise it is pow-
ered-up or it can be controlled by the Power
Management Module, respectively. Before
software can power-down the PLL in Active
mode by setting the PLLPWD bit, the FCLK bit
must be set. Attempting to set the PLLPWD
bit while the FCLK bit is clear is ignored. The
FCLK bit cannot be cleared until the PLL clock
has stabilized. After reset this bit is set.
0 – PLL is active.
1 – PLL is powered down.
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