CP3BT23 Datasheet, PDF (227/260 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

29.4 FLASH MEMORY ON-CHIP PROGRAMMING
(Guaranteed by design.)
Symbol
Parameter
Conditions
Min
Max Units
t_START
Program/Erase to NVSTR Setup Time^a
(NVSTR = Non-Volatile Storage
5
- µs
t_TRAN
NVSTR to Program Setup Time^b
10
- µs
t_PROG Programming Pulse Width^c
20
40 µs
t_PERASE Page Erase Pulse Width^d
20
- ms
t_MERASE Module Erase Pulse Width^e
200
- ms
t_END
NVSTR Hold Time^f
5
- µs
t_MEND
t_RCV
t_HV
t_HV
NVSTR Hold Time (Module Erase)^g
Recovery Time^h
Cumulative Program High Voltage Period For
Each Row After Eraseⁱ
Write/Erase Endurance
Data Retention
128K program blocks
8K data block
25°C
100
1
-
-
20,000
100
- µs
- µs
8 ms
4 ms
- cycles
- years
te a. Program/erase to NVSTR Setup Time is determined by the following equation:
t_START = T_clk × (FTDIV + 1) × (FTSTART + 1), where T_clk is the System Clock period, FTDIV is the contents of
the FMPSR or FSMPSR register, and FTSTART is the contents of the FMSTART or FSMSTART register
b. NVSTR to Program Setup Time is determined by the following equation:
t_TRAN = T_clk × (FTDIV + 1) × (FTTRAN + 1), where T_clk is the System Clock period, FTDIV is the contents of
le ^{the FMPSR or FSMPSR register, and FTTRAN is the contents of the FMTRAN or FSMTRAN register}
c. Programming Pulse Width is determined by the following equation:
t_PROG = T_clk × (FTDIV + 1) × 8 × (FTPROG + 1), where T_clk is the System Clock period, FTDIV is the con-
tents of the FMPSR or FSMPSR register, and FTPROG is the contents of the FMPROG or FSMPROG regis-
ter
d. Page Erase Pulse Width is determined by the following equation:
o _{tPERASE = Tclk × (FTDIV + 1) × 4096 × (FTPER + 1), where Tclk is the System Clock period, FTDIV is the}
contents of the FMPSR or FSMPSR register, and FTPER is the contents of the FMPERASE or FSMPER-
ASE register
s e. Module Erase Pulse Width is determined by the following equation:
t_MERASE = T_clk × (FTDIV + 1) × 4096 × (FTMER + 1), where T_clk is the System Clock period, FTDIV is the
contents of the FMPSR or FSMPSR register, and FTMER is the contents of the FMMERASE0 or
FSMMERASE0 register
b f. NVSTR Hold Time is determined by the following equation:
t_END = T_clk × (FTDIV + 1) × (FTEND + 1), where T_clk is the System Clock period, FTDIV is the contents of the
FMPSR or FSMPSR register, and FTEND is the contents of the FMEND or FSMEND register
g. NVSTR Hold Time (Module Erase) is determined by the following equation:
t_MEND = T_clk × (FTDIV + 1) × 8 × (FTMEND + 1), where T_clk is the System Clock period, FTDIV is the con-
O ^{tents of the FMPSR or FSMPSR register, and FTMEND is the contents of the FMMEND or FSMMEND regis-}
ter
h. Recovery Time is determined by the following equation:
t_RCV = T_clk × (FTDIV + 1) × (FTRCV + 1), where T_clk is the System Clock period, FTDIV is the contents of the
FMPSR or FSMPSR register, and FTRCV is the contents of the FMRCV or FSMRCV register
i. Cumulative program high voltage period for each row after erase t_HV is the accumulated duration a flash cell
is exposed to the programming voltage after the last erase cycle.
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