CP3BT23 Datasheet, PDF (244/260 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

29.14 EXTERNAL BUS TIMING
Table 85 External Bus Signals
Symbol Figure
Description
Reference
Min (ns)
Max (ns)
External Bus Input Signals
129,
t₁
131, Input Setup Time
132, D[15:0]
133
Before Rising Edge (RE)
on CLK
8
-
129,
t₂
131, Output Hold Time
132, D[15:0]
After RE on CLK
0
-
t₃
t₄
t₅
t₆
t₇
t₈
t₉
t₁₀
t₁₁
t₁₂
133
External Bus Output Signals
129, Output Valid Time
130 D[15:0]
129,
130,
te ^131,
132,
Output Valid Time
A[22:0]
133
129,
130,
131,
le ^132,
133
Output Active/Inactive Time
RD
SEL[1:0]
SELIO
129, Output Active/Inactive Time
130 WR[1:0]
o ¹³¹
Minimum Inactive Time
RD
After RE on CLK
After RE on CLK
After RE on CLK
After RE on CLK
At 2.0V
129
Output Float Time
D[15:0]
s _{129 Minimum Delay Time}
129,
130
Minimum Delay Time
b _{130 Minimum Delay Time}
129,
130,
131,
132,
O133
Output Hold Time
A[22:0]
D[15:0]
RD
SEL[2:0]
SELIO
After RE on CLK
From RD Trailing Edge
(TE) to D[15:0] driven
From RD TE to SELn
Leading Edge (LE)
From SELx TE to SELy LE
After RE on CLK
-
-
-
-
Tclk - 4
-
Tclk - 4
0
0
0
8
8
8
0.5 Tclk + 8
-
8
-
-
-
-
t₁₃
129, Output Hold Time
130 WR[1:0]
After RE on CLK
0.5 Tclk - 3
-
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