CP3BT23 Datasheet, PDF (51/260 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

10.4 MASKABLE INTERRUPT SOURCES
Table 20 shows the interrupts assigned to various on-chip
maskable interrupts. The priority of simultaneous maskable
interrupts is linear, with IRQ47 having the highest priority.
Table 20 Maskable Interrupts Assignment
IRQ Number
Description
IRQ Number
Description
IRQ14
IRQ13
IRQ12
Reserved
ADC (Done)
MIWU Interrupt 0
IRQ47
IRQ46
IRQ45
IRQ44
IRQ43
IRQ42
IRQ41
IRQ40
IRQ39
IRQ38
IRQ37
IRQ36
IRQ35
IRQ34
IRQ33
IRQ32
IRQ31
IRQ30
IRQ29
IRQ28
IRQ27
IRQ26
IRQ25
IRQ24
IRQ23
IRQ11
MIWU Interrupt 1
TWM (Timer 0)
IRQ10
MIWU Interrupt 2
Bluetooth LLC 0
IRQ9
MIWU Interrupt 3
Bluetooth LLC 1
IRQ8
MIWU Interrupt 4
Bluetooth LLC 2
IRQ7
MIWU Interrupt 5
Bluetooth LLC 3
Bluetooth LLC 4
Bluetooth LLC 5
Reserved
DMA Channel 0
te ^{DMA Channel 1}
DMA Channel 2
DMA Channel 3
CAN0
le ^{Advanced Audio Interface (AAI)}
UART0 RX
CVSD/PCM Converter
ACCESS.bus
o _{TA (Timer input A)}
TB (Timer input B)
s _{VTUA (VTU Interrupt Request 1)}
VTUB (VTU Interrupt Request 2)
VTUC (VTU Interrupt Request 3)
b _{VTUD (VTU Interrupt Request 4)}
Microwire/SPI RX/TX
O^{UART0 TX}
IRQ6
IRQ5
IRQ4
IRQ3
IRQ2
IRQ1
IRQ0
MIWU Interrupt 6
MIWU Interrupt 7
Reserved
Random Number Generator (RNG)
Reserved
Flash Program/Data Memory
Reserved
All reserved interrupt vectors should point to default or error
interrupt handlers.
10.5 NESTED INTERRUPTS
Nested NMI interrupts are always enabled. Nested
maskable interrupts are disabled by default, however an in-
terrupt handler can allow nested maskable interrupts by set-
ting the I bit in the PSR. The LPR instruction is used to set
the I bit.
Nesting of specific maskable interrupts can be allowed by
disabling interrupts from sources for which nesting is not al-
lowed, before setting the I bit. Individual maskable interrupt
sources can be disabled using the IENAM0 and IENAM1
registers.
Any number of levels of nested interrupts are allowed, limit-
ed only by the available memory for the interrupt stack.
IRQ22
UART0 CTS
IRQ21
CAN1
IRQ20
UART1 RX
IRQ19
UART1 TX
IRQ18
UART2 RX
IRQ17
UART2 TX
IRQ16
UART3 RX
IRQ15
UART3 TX
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