CP3BT23 Datasheet, PDF (43/260 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

Direct mode supports two bus policies: intermittent and con- 9.3
OPERATION MODES
tinuous. In intermittent mode, the DMAC gives bus master-
ship back to the CPU after every cycle. In continuous mode,
the DMAC remains bus master until the transfer is complet-
The DMAC operates in three different block transfer modes:
single transfer, double buffer, and auto-initialize.
ed. The maximum bus throughput in intermittent mode is 9.3.1 Single Transfer Operation
one transfer for every three System Clock cycles. The max- _{This mode provides the simplest way to accomplish a single}
imum bus throughput in continuous mode is one transfer for _{block data transfer.}
every clock cycle.
The I/O device which made the DMA request is called the
implied I/O device. The other device can be either memory
or another I/O device, and is called the addressed device.
Initialization
1. Write the block transfer addresses and byte count into
the corresponding ADCAn, ADCBn, and BLTCn
counters.
Because only one address is required in direct mode, this _{2. Clear the DMACNTLn.OT bit to select non-auto-initial-}
address is taken from the corresponding ADCAn counter.
ize mode. Clear the DMASTAT.VLD bit by writing a 1 to
The DMAC channel generates either a read or a write bus
it.
cycle, as controlled by the DMACNTLn.DIR bit.
When the DMACNTLn.DIR bit is clear, a read bus cycle
from the addressed device is performed, and the data is
written to the implied I/O device. When the DMACNTLn.DIR
bit is set, a write bus cycle to the addressed device is per-
formed, and the data is read from the implied I/O device.
The configuration of either address freeze or address up-
te ^{date (increment or decrement) is independent of the num-}
ber of transferred bytes, transfer direction, or number of
bytes in each DMAC transfer cycle. All these can be config-
ured for each channel by programming the appropriate con-
trol register.
Whether 8 or 16 bits are transferred in each cycle is select-
le ^{ed by the DMACNTLn.TCS register bit. After the data item}
has been transferred, the BLTCn counter is decremented by
one. The ADCAn counter is updated according to the INCA
and ADA fields in the DMACNTLn register.
9.2.2 Indirect (Memory-To-Memory) Transfers
o ^{In indirect (memory-to-memory) mode, data transfers use}
two consecutive bus cycles. The data is first read into a tem-
porary register, and then written to the destination in the fol-
lowing cycle. This mode is slower than the direct (flyby)
s mode, but it provides support for different source and desti-
nation bus widths. Indirect mode must be used for transfers
between memory devices.
If an intermittent bus policy is used, the maximum through-
b put is one transfer for every five clock cycles. If a continuous
bus policy is used, maximum throughput is one transfer for
every two clock cycles.
When the DMACNTLn.DIR bit is 0, the first bus cycle reads
O ^{data from the source using the ADCAn counter, while the}
3. Set the DMACNTLn.CHEN bit to activate the channel
and enable it to respond to DMA transfer requests.
Termination
When the BLTCn counter reaches 0:
1. The transfer operation terminates.
2. The DMASTAT.TC and DMASTAT.OVR bits are set, and
the DMASTAT.CHAC bit is cleared.
3. An interrupt is generated if enabled by the
DMACNTLn.ETC or DMACNTLn.EOVR bits.
The DMACNTLn.CHEN bit must be cleared before loading
the DMACNTLn register to avoid prematurely starting a new
DMA transfer.
9.3.2 Double Buffer Operation
This mode allows software to set up the next block transfer
while the current block transfer proceeds.
Initialization
1. Write the block transfer addresses and byte count into
the ADCAn, ADCBn, and BLTCn counters.
2. Clear the DMACNTLn.OT bit to select non-auto-initial-
ize mode. Clear the DMASTAT.VLD bit by writing a 1 to
it.
3. Set the DMACNTLn.CHEN bit. This activates the chan-
nel and enables it to respond to DMA transfer requests.
4. While the current block transfer proceeds, write the ad-
dresses and byte count for the next block into the
ADRAn, ADRBn, and BLTRn registers. The BLTRn reg-
ister must be written last, because it sets the DMAS-
TAT.VLD bit which indicates that all the parameters for
the next transfer have been updated.
Continuation/Termination
second bus cycle writes the data into the destination using
the ADCBn counter. When the DMACNTLn.DIR bit is set,
When the BLTCn counter reaches 0:
the first bus cycle reads data from the source using the AD- ^{1. The DMASTAT.TC bit is set.}
CBn counter, while the second bus cycle writes the data into ^{2. An interrupt is generated if enabled by the}
the destination addressed by the ADCAn counter.
DMACNTLn.ETC bit.
The number of bytes transferred in each cycle is taken from ^{3. The DMAC channel checks the value of the VLD bit.}
the DMACNTLn.TCS register bit. After the data item has ^{If the DMASTAT.VLD bit is set:}
been transferred, the BLTCn counter is decremented by
one. The ADCAn and ADCBn counters are updated accord-
ing to the INCA, INCB, ADA, and ADB fields in the
1. The channel copies the ADRAn, ADRBn, and BLTRn
values into the ADCAn, ADCBn, and BLTCn registers.
2. The DMASTAT.VLD bit is cleared.
DMACNTLn register.
3. The next block transfer is started.
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