CP3BT23 Datasheet, PDF (129/260 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

On the receiver side, only the valid data bits which were re- port enabled for slots 0 and 1 in receive and transmit direc-
ceived during the slots assigned to this interface are copied tion.
into the receive FIFO or DMA registers. The assignment of
slots to the receiver is specified by the Receive Slot Assign-
ment bits (RXSA) in the ATCR register. It can also be spec-
ARDR 0
DMA
Request 1
ified whether the received data is copied into the receive SRD
FIFO or into the corresponding DMA receive register. There
ARSR
ARDR 1
DMA
Request 3
is one DMA receive register (ARDRn) for each of the maxi-
mum four data slots. Each slot may be configured individu-
ally.
DMA Slot
Slot ^{1 data}
ARDR 2
Assignment
Figure 65 shows the frame timing while operating in network
mode with four slots per frame, slot 1 assigned to the inter-
face, and a long frame sync interval.
Slot _{2 and 3 data}
ARDR 3
RX
IRQ
FIFO
Long Frame Sync
(SFS/SRFS)
Shift Data
(STD/SRD)
Data
(ignored)
Data
(valid)
High-impedance
Data
(ignored)
Slot0
Slot1
Unused Slots
te ^Frame
DS055
Figure 65. Network Mode Frame
IRQ Support
le ^{If DMA is not enabled for a receive slot n (RXDSAn = 0), all}
data received in this slot is loaded into the receive FIFO. An
IRQ is asserted as soon as the number of data bytes or
words in the receive FIFO is greater than a configured warn-
ing limit.
If DMA is not enabled for a transmit slot n (TXDSAn = 0), all
o _{data to be transmitted in this slot are read from the transmit}
FIFO. An IRQ is asserted as soon as the number data bytes
or words available in the transmit FIFO is equal or less than
a configured warning limit.
s _{DMA Support}
If DMA support is enabled for a receive slot n (RXDSA0 =
1), all data received in this slot is only transferred from the
b ^{ARSR into the corresponding DMA receive register}
(ARDRn). A DMA request is asserted when the ARDRn reg-
ister is full.
If DMA is enabled for a transmit slot n (TXDSAn = 1), all data
to be transmitted in slot n are read from the corresponding
O ^{DMA transmit register (ATDRn). A DMA request is asserted}
STD
ATSR
DMA Slot
Assignment
Slot ^{1 data}
Slot _{2 and 3 data}
ATDR 0
ATDR 1
DMA
Request 0
DMA
Request 2
ATDR 2
ATDR 3
TX
FIFO
IRQ
DS056
Figure 66. IRQ/DMA Support in Network Mode
If the interface operates in synchronous mode, the receiver
uses the transmit bit clock (SCK) and transmit frame sync
signal (SFS). This allows the pins used for the receive bit
clock (SRCLK) and receive frame sync (SRFS) to be used
as additional frame sync signals in network mode. The extra
frame sync signals are useful when the audio interface com-
municates to more than one codec, because codecs typical-
ly start transmission immediately after the frame sync pulse.
The SRCLK pin is driven with a frame sync pulse at the be-
ginning of the second slot (slot 1), and the SRFS pin is driv-
en with a frame sync pulse at the beginning of slot 2.
Figure 67 shows a frame timing diagram for this configura-
tion, using the additional frame sync signals on SRCLK and
SRFS to address up to three devices.
to the DMA controller when the ATDRn register is empty.
Figure 66 illustrates the data flow for IRQ and DMA support
in network mode, using four slots per frame and DMA sup-
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