CP3BT23 Datasheet, PDF (154/260 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

UPEN
The Parity Enable bit enables or disables par- UERD
The Enable Receive DMA bit controls whether
ity generation and parity checking. When the
DMA is used for UART receive operations.
UART is configured to transmit nine data bits
Enabling receive DMA automatically disables
per frame, there is no parity bit and the Un-
receive interrupts, without regard to the state
PEN bit is ignored.
of the UERI bit. Receive error interrupts are
0 – Parity generation and checking disabled.
unaffected by the UERD bit.
1 – Parity generation and checking enabled.
0 – Receive DMA disabled.
21.3.6 UART Mode Select Register 1 (UnMDSL1)
UFCE
1 – Receive DMA enabled.
The Flow Control Enable bit controls whether
The UnMDSL1 register is a byte-wide, read/write register
flow control interrupts are enabled.
that selects the clock source, synchronization mode, atten-
0 – Flow control interrupts disabled.
tion mode, and line break generation. This register is
1 – Flow control interrupts enabled.
cleared at reset. The register format is shown below.
URTS
The Ready To Send bit directly controls the
state of the RTS output.
7
6
5
4
3
2
1
0
0 – RTS output is high.
1 – RTS output is low.
URTS UFCE UERD UETD UCKS UBRK UATN UMOD
21.3.7 UART Status Register (UnSTAT)
UMOD
te ^UATN
le _UBRK
Obso ^UCKS
The Mode bit selects between synchronous
and asynchronous mode. Synchronous mode
is only available for the UART0 module.
0 – Asynchronous mode.
1 – Synchronous mode.
The Attention Mode bit is used to enable At-
tention mode. When set, this bit selects the at-
tention mode of operation for the UART. When
clear, the attention mode is disabled. The
hardware clears this bit after an address
frame is received. An address frame is a 9-bit
character with a 1 in the ninth bit position.
0 – Attention mode disabled.
1 – Attention mode enabled.
The Force Transmission Break bit is used to
force the TXD output low. Setting this bit to 1
causes the TXD pin to go low. TXD remains
low until the UBRK bit is cleared by software.
0 – Normal operation.
1 – TXD pin forced low.
The Synchronous Clock Source bit controls
the clock source when the UART operates in
the synchronous mode (UMOD = 1). This
functionality is only available for the UART0
module. If the UCKS bit is set, the UART op-
erates from an external clock provided on the
CKX pin. If the UCKS bit is clear, the UART
operates from the baud rate clock produced
by the UART on the CKX pin. This bit is ig-
nored when the UART operates in the asyn-
The UnSTAT register is a byte-wide, read-only register that
contains the receive and transmit status bits. This register is
cleared upon reset. Any attempt by software to write to this
register is ignored. The register format is shown below.
7
6
5
4
3
2 10
Res. UXMIP URB9 UBKD UERR UDOE UFE UPE
UPE
UFE
UDOE
The Parity Error bit indicates whether a parity
error is detected within a received character.
This bit is automatically cleared by the hard-
ware when the UnSTAT register is read.
0 – No parity error occurred.
1 – Parity error occurred.
The Framing Error bit indicates whether the
UART fails to receive a valid stop bit at the end
of a frame. This bit is automatically cleared by
the hardware when the UnSTAT register is
read.
0 – No framing error occurred.
1 – Framing error occurred.
The Data Overrun Error bit is set when a new
character is received and transferred to the
UnRBUF register before software has read
the previous character from the UnRBUF reg-
ister. This bit is automatically cleared by the
hardware when the UnSTAT register is read.
0 – No receive overrun error occurred.
1 – Receive overrun error occurred.
chronous mode.
UERR
The Error Status bit indicates when a parity,
0 – Internal baud rate clock is used.
framing, or overrun error occurs (any time that
1 – External clock is used.
the UPE, UFE, or UDOE bit is set). It is auto-
UETD
The Enable Transmit DMA bit controls wheth-
matically cleared by the hardware when the
er DMA is used for UART transmit operations.
UPE, UFE, and UDOE bits are all 0.
Enabling transmit DMA automatically disables
0 – No receive error occurred.
transmit interrupts, without regard to the state
1 – Receive error occurred.
of the UETI bit.
0 – Transmit DMA disabled.
1 – Transmit DMA enabled.
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