CP3BT23 Datasheet, PDF (257/260 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

31.0 Revision History
Table 88 Revision History
Date
4/3/03
5/26/03
6/16/03
6/30/03
10/7/03
11/14/03
2/28/04
3/16/04
5/10/04
5/12/04
6/2/04
Table 88 Revision History
Date
Major Changes From Previous Version
Major Changes From Previous Version
6/15/04
Changed absolute maximum supply voltage
to 3.6V. Changed Preliminary to Final.
Original release.
Added AC timing specifications for
Fixed maximum boot area in Section 8.
Fixed names of clock signals in Figures 5
7/16/04
ACCESS.bus, external bus, GPIO,
Microwire/SPI, and UART. Corrected
and 6. Fixed addresses of FSMARx
address of flash data memory in Section 8.
registers in Register Map section. Added
default value for RNGDIV.
Added conditions which clear the ACBST,
ACBCST, and ACBCTL1 registers. Added
Corrected Table 27. Changed I_OH and I_OL.
Changed NSIDs, deleted commercial
temperature range device, changed ADC
conversion time to 15 microseconds.
Updated DC electrical specifications.
Added ADC electrical specifications. Added
more detail to Table 7. Added Table 25.
te ^{Defined valid range of SCDV field in}
Microwire/SPI module. Noted default
PRSSC register value generates a Slow
Clock frequency slightly higher than 32768
Hz. Clarified usage of CVSTAT register bits
and fields in CVSD/PCM module. Updated
layout of Bluetooth LLC registers. Added
le ^{usage hint for avoiding ACCESS.bus}
module bus error. Added usage hint for
avoiding CAN unexpected loopback
condition.
Changed NSID designations in the product
o selection guide. Updated Bluetooth section
for LMX5251 and LMX5252 radio chips.
Added BTSEQ[3:1] signals to pin
descriptions, GPIO alternate functions, and
s _{package pin assignments. Added entry for}
CTIM register in CAN section register list.
Changed CVSD Conversion section.
Changed definition of the RESOLUTION
b ^{field of the CVSD Control register}
(CVCTRL). Changed reset values for ADC
registers. Added maximum I/O voltage in
Absolute Maximum Ratings section. Added
RESET Low minimum DC specification.
O^{Added Iccprog DC specification. Changed}
11/9/04
4/4/05
9/24/06
2/21/07
external reset as condition which clears
WDRST and ISPRST bits in the MSTAT
register. Inverted sense of PEN_DOWN bit
in the ADCRESLT register.
Added new reset circuits. Added note about
fluctuations in response due to SDI activity.
New back page.
Added 14-bit counter delay to external
reset.
Updated NSIDs.
Vxl2 DC specification.
Changed LMX5251 interface circuit.
Updated DC specifications for clock input
low voltage, reset input high voltage, and
halt current.
Corrected NSIDs for no-lead solder parts.
Moved revision history in front of physical
dimensions. Changed back page
disclaimers.
Changed AC and DC specifications.
www.national.com
256