CP3BT23 Datasheet, PDF (135/260 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

19.6.6 Freeze Mode
19.7 AUDIO INTERFACE REGISTERS
The audio interface provides a FREEZE input, which allows
to freeze the status of the audio interface while a develop-
ment system examines the contents of the FIFOs and reg-
Table 60 Audio Interface Registers
isters.
When the FREEZE input is asserted, the audio interface be-
Name
Address
Description
haves as follows:
! The receive FIFO or receive DMA registers are not up-
ARFR
FF FD40h
Audio Receive FIFO
Register
dated with new data.
! The receive status bits (RXO, RXE, RXF, and RXAF) are
not changed, even though the receive FIFO or receive
ARDR0
FF FD42h
Audio Receive DMA
Register 0
DMA registers are read.
! The transmit shift register (ATSR) is not updated with
ARDR1
FF FD44h
Audio Receive DMA
Register 1
new data from the transmit FIFO or transmit DMA regis-
ters.
! The transmit status bits (TXU, TXF, TXE, and TXAE) are
not changed, even though the transmit FIFO or transmit
DMA registers are written.
The time at which these registers are frozen will vary be-
cause they operate from a different clock than the one used
Obsolete ^{to generate the freeze signal.}
ARDR2
ARDR3
ATFR
ATDR0
ATDR1
ATDR2
ATDR3
AGCR
AISCR
ARSCR
ATSCR
ACCR
ADMACR
FF FD46h
FF FD48h
FF FD4Ah
FF FD4Ch
FF FD4Eh
FF FD50h
FF FD52h
FF FD54h
FF FD56h
FF FD58h
FF FD5Ah
FF FD5Ch
FF FD5Eh
Audio Receive DMA
Register 2
Audio Receive DMA
Register 3
Audio Transmit FIFO
Register
Audio Transmit DMA
Register 0
Audio Transmit DMA
Register 1
Audio Transmit DMA
Register 2
Audio Transmit DMA
Register 3
Audio Global
Configuration Register
Audio Interrupt Status
and Control Register
Audio Receive Status
and Control Register
Audio Transmit Status
and Control Register
Audio Clock Control
Register
Audio DMA Control
Register
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