CP3BT23 Datasheet, PDF (180/260 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

25.0 Multi-Function Timer
The Multi-Function Timer module contains a pair of 16-bit ! Single-Input Capture and Single Timer mode, which pro-
timer/counters. Each timer/counter unit offers a choice of vides one external event counter and one system timer.
clock sources for operation and can be configured to oper- _{The timer unit uses two I/O pins, called TA and TB. The tim-}
ate in any of the following modes:
er I/O pins are alternate functions of the PG7 and PE4 port
! Processor-Independent Pulse Width Modulation (PWM) pins, respectively.
mode, which generates pulses of a specified width and
duty cycle, and which also provides a general-purpose
25.1
TIMER STRUCTURE
timer/counter.
Figure 95 is a block diagram showing the internal structure
! Dual-Input Capture mode, which measures the elapsed of the MFT. There are two main functional blocks: a Timer/
time between occurrences of external events, and which Counter and Action block and a Clock Source block. The
also provides a general-purpose timer/counter.
Timer/Counter and Action block contains two separate tim-
! Dual Independent Timer mode, which generates system er/counter units, called Timer/Counter 1 and Timer/Counter
timing signals or counts occurrences of external events. 2.
System
lete ^Clock
Clock Source
Timer/Counter
Reload/Capture A
TCRA
Action
Timer/Counter 1
TCNT1
Reload/Capture B
TCRB
Timer/Counter 2
TCNT2
External Event
PWM/Capture/Counter
Mode Select + Control
TA
Interrupt A
Interrupt B
TB
DS081
Figure 95. Multi-Function Timer Block Diagram
25.1.1 Timer/Counter Block
The Timer/Counter block contains the following functional
o ^blocks:
! Two 16-bit counters, Timer/Counter 1 (TCNT1) and Tim-
er/Counter 2 (TCNT2)
! Two 16-bit reload/capture registers, TCRA and TCRB
s ! Control logic necessary to configure the timer to operate
in any of the four operating modes
! Interrupt control and I/O control logic
In a power-saving mode that uses the low-frequency
(32.768 kHz) clock as the System Clock, the synchroniza-
tion circuit requires that the Slow Clock operate at no more
than one-fourth the speed of the 32.768 kHz System Clock.
25.1.2 Clock Source Block
The Clock Source block generates the signals used to clock
the two timer/counter registers. The internal structure of the
Clock Source block is shown in Figure 96.
Ob ^Reset
Prescaler Register
TPRSC
5-Bit
No Clock
Prescaled Clock
Counter 1
Clock
Select
Counter 1
Clock
System
Prescaler Counter
Clock
TB
Synchr.
Pulse Accumulator
External Event
Counter 2
Clock
Select
Counter 2
Clock
DS082
Figure 96. Multi-Function Timer Clock Source
179
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