CP3BT23 Datasheet, PDF (162/260 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

22.3 SLAVE MODE
22.4 INTERRUPT GENERATION
In Slave mode, the MSK pin is an input for the shift clock Interrupts may be enabled for any of the conditions shown
MSK. MDIDO is placed in TRI-STATE mode when MWCS is in Table 66.
inactive. Data transfer is enabled when MWCS is active.
Table 66 Microwire Interrupt Trigger Condition
The slave starts driving MDIDO when MWCS is active. The
most significant bit (lower byte in 8-bit mode or upper byte
in 16-bit mode) is output onto the MDIDO pin first. After
eight or sixteen clocks (depending on the selected mode),
the data transfer is completed.
If a new shift process starts before MWDAT was written, i.e.,
Condition
Status
Bit in the
MWSTAT
Register
Interrupt
Enable Bit
in the
MWCTRL1
Register
Description
while MWDAT does not contain any valid data, and the
ECHO bit is set, the data received from MDODI is transmit-
ted on MDIDO in addition to being shifted to MWDAT. If the
ECHO bit is clear, the data transmitted on MDIDO is the
Not Busy
BSY
The shifter is ready
EIW for the next data
transfer sequence.
data held in the MWDAT register, regardless of its validity.
The master may negate the MWCS signal to synchronize
the bit count between the master and the slave. In the case
that the slave is the only slave in the system, MWCS can be
te ^{tied to ground.}
Read
Buffer Full
Overrun
RBF
OVF
The read buffer is
EIR full and waiting to be
unloaded.
A new data transfer
sequence started
EIO while both the shifter
and the read buffer
were full.
Figure 87 illustrates the interrupt generation logic of this
module.
EIO
le^{OVR = 1}
EIR
RBF = 1
o _EIW
MWSPI
Interrupt
s _BSY=0
DS073
Ob ^{Figure 87. MWSPI Interrupts}
161
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