TI380C30A Datasheet, PDF (9/81 Pages) Texas Instruments – INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE

TI380C30A
INTEGRATED TOKEN-RING COMMPROCESSOR
AND PHYSICAL-LAYER INTERFACE
SPWS034 – MARCH 1998
Terminal Functions (Continued)
TERMINAL
NAME
NO.
I/O/E†
DESCRIPTION
Column-address strobe for DRAMs. The column address is valid for 3/16ths of the memory cycle
following the row-address portion of the cycle. MCAS is driven low every memory cycle while the column
address is valid on MADL0–MADL7, MAXPH, and MAXPL, except when one of the following conditions
occurs:
MCAS
18
O
– When the address accessed is in the BIA ROM (>00.0000–>00.000F)
– When the address accessed is in the EPROM memory map (that is, when the BOOT bit in the SIFACL
register is 0 and an access is made between >00.0010 and >00.FFFF or >1F.0000 and >1F.FFFF)
– When the cycle is a refresh cycle, in which case MCAS is driven low at the start of the cycle before MRAS
[for DRAMs that have CAS-before-RAS refresh]. For DRAMs that do not support CAS-before-RAS
refresh, it may be necessary to disable MCAS with MREF during the refresh cycle.
MDDIR
Data direction. MDDIR is used as a direction control for bidirectional bus drivers. MDDIR becomes valid
before MBEN becomes active.
15
I/O
H = TI380C30A memory-bus write
L = TI380C30A memory-bus read
MOE
Memory-output enable. MOE enables the outputs of the DRAM memory during a read cycle. MOE is high
for EPROM or BIA ROM read cycles.
23
O
H = Disable DRAM outputs
L = Enable DRAM outputs
MRAS
Row-address strobe for DRAMs. The row address lasts for the first 5/16ths of the memory cycle. MRAS
20
O
is driven low every memory cycle while the row address is valid on MADL0–MADL7, MAXPH, and MAXPL
for both RAM and ROM cycles. MRAS is also driven low during refresh cycles when the refresh address
is valid on MADL0–MADL7.
MREF
DRAM refresh cycle in progress. MREF indicates that a DRAM refresh cycle is occurring. It is also used
for disabling MCAS to all DRAMs that do not use a CAS-before-RAS refresh.
1
O
H = DRAM refresh cycle in process
L = Not a DRAM refresh cycle
MRESET
Memory-bus reset. MRESET is a reset signal generated when either the ARESET bit in the SIFACL
register is set or SRESET is asserted. MRESET is used for resetting external local-bus glue logic.
175
O
H = External logic not reset
L = External logic reset
MROMEN
ROM enable. During the first 5/16ths of the memory cycle, MROMEN is used to provide a chip select for
ROMs when the BOOT bit of the SIFACL is 0 (that is, when code is resident in ROM, and not RAM).
MROMEN can be latched by MAL. MROMEN goes low for any read from addresses >00.0010–>00.FFFF
or >1F.0000–>1F.FFFF when the BOOT bit in the SIFACL register is 0. MROMEN stays high for writes
to these addresses, accesses of other addresses, or accesses of any address when the BOOT bit is 1.
4
O
During the final three-fourths of the memory cycle, MROMEN outputs the A13 address signal for
interfacing to a BIA ROM. This means MBIAEN, MAX0, MROMEN, and MAX2 form a glueless interface
for the BIA ROM.
H = ROM disabled
L = ROM enabled
Local-memory write. MW is used to specify a write cycle on the local-memory bus. The data on the MADH
and MADL buses is valid while MW is low. DRAMs latch data on the falling edge of MW, while SRAMs
MW
19
O
latch data on the rising edge of MW.
H = Not a local-memory write cycle
L = Local-memory write cycle
NABL
156
I
Output-enable control. NABL is used in the physical-layer circuitry (see Note 1).
NC
135
166
These NC pins must be left unconnected.
NMI
55
I
Nonmaskable interrupt request. NMI must be left unconnected.
† _{I = input, O = output, E = provides external-component connection to the internal circuitry for tuning}
NOTE 1. Terminal has an internal pullup device to maintain a high-voltage level when left unconnected (no etch).
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