TI380C30A Datasheet, PDF (61/81 Pages) Texas Instruments – INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE

TI380C30A
INTEGRATED TOKEN-RING COMMPROCESSOR
AND PHYSICAL-LAYER INTERFACE
SPWS034 – MARCH 1998
TWAIT
T4
TX†
T1
T2
V
T3
T4
T1
SBCLK
SBHE‡ ^{ÌÌÌÌÌÌÌÌÌÌÌÌÌÌ2ÌÌ12 ÌÌÌÌ}
Valid
ÌÌÌÌÌÌ
High
SRD
227W
223W
SWR
216
217
217
SXAL
SALE
SADH0–SADH7
SADL0–SADL7
SPH
SPL§
216
233
212
218
Extended
Address
219
212
218
233
Address
208a
216a
221
Output Data
SRDY
SDBEN
237W
208b
225WH
225W
SDDIR
High
† _{In cycle-steal mode, state TX is present on every system bus transfer. In burst mode, state TX is present on the first bus transfer and whenever}
the increment of the DMA address register carries beyond the least significant 16 bits.
‡ _{In 8-bit 80x8x mode, SBHE/SRNW is a don’t care input during DIO and an inactive (high) output during DMA.}
§ _{In 8-bit 80x8x mode, the most significant byte of the address is maintained on SADH for T2, T3, and T4. The address is maintained according}
to parameter 221; that is, held after T4 high.
Figure 25. 80x8x-Mode DMA Write Cycle
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