TI380C30A Datasheet, PDF (17/81 Pages) Texas Instruments – INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE

TI380C30A
INTEGRATED TOKEN-RING COMMPROCESSOR
AND PHYSICAL-LAYER INTERFACE
SPWS034 – MARCH 1998
Terminal Functions (Continued)
TERMINAL
NAME NO.
I/O/E†
DESCRIPTION
XMT+
XMT–
143
144
E
Transmit differential outputs. XMT+ and XMT– provide a low-impedance differential source for line drive by
way of filtering and transformer isolation.
XT1
130
I
XTAL connection. An 8-MHz crystal network can be connected here to provide a reference clock for the
XT2
132
E
TI380C30A. Alternatively, an 8-MHz TTL clock source can be connected to XT1.
† _{I = input, O = output, E = provides external-component connection to the internal circuitry for tuning}
architecture
The major blocks of the TI380C30A include the CP, SIF, MIF, PH, CG, ASF, and PHY. The functionality of each
block is described in the following sections.
communications processor (CP)
The CP performs the control and monitoring of the other functional blocks in the TI380C30A. The control and
monitoring protocols are specified by the software (downloaded or ROM-based) in local memory. Available
protocols include:
D Media access control (MAC) software
D Logical link control (LLC) software
D Copy all frames (CAF) software
The CP is a proprietary 16-bit central processing unit (CPU) with data cache and a single prefetch pipe for
pipelining of instructions. These features enhance the TI380C30A maximum performance capability to about
8 million instructions per second (MIPS), with an average of about 5 MIPS.
system interface (SIF)
The SIF performs the interfacing of the LAN subsystem to the host system. This interface can require additional
logic depending on the application. The system interface can transfer information/data using any of these three
methods:
D Direct memory access (DMA)
D Direct input/output (DIO)
D Pseudo-direct memory access (PDMA)
DMA (or PDMA) is used to transfer all data to/from host memory from/to local memory. The main uses of DIO
are loading the software to local memory and initializing the TI380C30A. DIO also allows command/status
interrupts to occur to and from the TI380C30A.
The system interface can be hardware-selected for either of two modes by using SI/M. The mode selected
determines the memory organizations and control signals used. These modes are:
D The Intel mode (80x8x families): 8-, 16-, and 32-bit bus devices
D The Motorola mode (68xxx microprocessor family): 16- and 32-bit bus devices
The system interface supports host-system memory addressing up to 32 bits (32-bit reach into the host system
memory). This allows greater flexibility in using/accessing host-system memory. System designers are allowed
to customize the system interface to their particular bus by:
D Programmable burst transfers or cycle-steal DMA operations
D Optional parity protection
These features are implemented in hardware to reduce system overhead, facilitate automatic rearbitration of
the bus after a burst, or repeat a cycle when errors occur (parity or bus). Bus retries are also supported.
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