TI380C30A Datasheet, PDF (10/81 Pages) Texas Instruments – INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE

TI380C30A
INTEGRATED TOKEN-RING COMMPROCESSOR
AND PHYSICAL-LAYER INTERFACE
SPWS034 – MARCH 1998
Terminal Functions (Continued)
TERMINAL
NAME
NO.
I/O/E†
DESCRIPTION
Network selection outputs. NSELOUT0 and NSELOUT1 are controlled by the host through the
corresponding bits of the SIFACL register. The value of NSELOUT0 and NSELOUT1 can be changed
NSELOUT0
NSELOUT1
58
171
O
only while the TI380C30A is reset.
NSELOUT0 NSELOUT1
Description
L
H
16-Mbit/s token ring
H
H
4-Mbit/s token ring
NSRT
Insert control. NSRT enables the phantom-driver outputs (PHOUTA and PHOUTB) through the watchdog
timer for insertion onto the token ring.
121
O
Static high = Inactive, phantom current removed (due to watchdog timer)
Static low = Inactive, phantom current removed (due to watchdog timer)
Falling edge = Active, current output on PHOUTA and PHOUTB
OSC32
5
O
Oscillator output. OSC32 provides a 32-MHz clock output and can be used to drive OSCIN and one other
TTL load.
OSCIN
External oscillator input. OSCIN provides the clock frequency to the TI380C30A for a 4-MHz or 6-MHz
internal bus (see Notes 5, 6, and 8).
6
I
CLKDIV OSCIN
H
64 MHz for a 4-MHz local bus
L
32 MHz for a 4-MHz local bus or 48 MHz for a 6-MHz local bus
Oscillator output
OSCOUT
172
O
CLKDIV
L
H
OSCOUT
OSCIN ÷ 4
OSCIN ÷ 8
(if OSCIN = 32 MHz, OSCOUT = 8 MHz)
(if OSCIN = 48 MHz, OSCOUT = 12 MHz)
(if OSCIN = 64 MHz, OSCOUT = 8 MHz)
PHOUTA
PHOUTB
139
141
O
Phantom-driver outputs A and B. PHOUTA and PHOUTB cause insertion onto the token ring. PHOUTA
and PHOUTB should be connected to the center tap of the transmit transformer secondary winding for
phantom-drive generation.
PRTYEN
Parity enable. The value on PRTYEN is loaded into the PEN bit of the SIFACL register at reset (that is,
when SRESET is asserted or the ARESET bit in the SIFACL register is set) to form a default value.
59
I
PRTYEN enables parity checking for the local memory.
H = Local-memory data bus checked for parity (see Note 1)
L = Local-memory data bus not checked for parity.
Power-down control (see Note 7)
PWRDN
154
I
H = Normal operation
L = TI380C30A physical-layer circuitry is placed into a power-down state. All TTL outputs of the physical
layer are driven to the high-impedance state.
PXTAL
163
O
Reference-clock output. PXTAL is synthesized from the 8-MHz crystal oscillator used for XT1 and XT2.
For 16 Mbit/s, it is a 32-MHz clock; for 4 Mbit/s, it is an 8-MHz clock (see Note 8).
RATER
158
O
RATER indicates that there are transitions on the RCV+/RCV– input pair (DRVR+/DRVR– if WRAP is as-
serted low) but that the transition rate is not consistent with the ring speed selected by the S4/16 pin.
RCLK
161
O
Recovered clock. RCLK is the clock recovered from the token-ring received data. For 16-Mbit/s operation,
it is a 32-MHz clock. For 4-Mbit/s operation, it is an 8-MHz clock.
RCV+
RCV–
149
147
I
Receiver. RCV+ and RCV– are differential inputs that receive the token-ring data by way of isolation
transformers.
RCVR
162
O
Recovered data. RCVR contains the data recovered from the token ring.
† _{I = input, O = output, E = provides external-component connection to the internal circuitry for tuning}
NOTES: 1. Terminal has an internal pullup device to maintain a high-voltage level when left unconnected (no etch).
5. Terminal has an expanded input voltage specification.
6. A maximum of two TI380C30A devices can be connected to any one oscillator.
7. Terminal should be tied to VDD with a 4.7-kΩ pullup resistor.
8. A BUD 35 failure can occur if the rising edge of PXTAL occurs 5 ns to 9 ns after the rising edge of OSCIN. It is a BUD problem only,
and does not affect normal operation.
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