TI380C30A Datasheet, PDF (48/81 Pages) Texas Instruments – INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE

TI380C30A
INTEGRATED TOKEN-RING COMMPROCESSOR
AND PHYSICAL-LAYER INTERFACE
SPWS034 – MARCH 1998
memory-bus timing (continued)
t_M is the cycle time of one-eighth of a local-memory cycle (31.25 ns minimum for a 4-MHz local bus or 20.83 ns
minimum for a 6-MHz local bus).
DRAM-refresh cycle (see Figure 15)
NO.
15 Setup time, row address on MADL0–MADL7, MAXPH, and MAXPL before MRAS no longer high
16 Hold time, row address on MADL0–MADL7, MAXPH, and MAXPL after MRAS no longer high
18 Pulse duration, MRAS low
19 Pulse duration, MRAS high
73a Setup time, MCAS low before MRAS no longer high
73b Hold time, MCAS low after MRAS low
73c Setup time, MREF high before MCAS no longer high
73d Hold time, MREF high after MCAS high
MIN
1.5tM–11.5
tM–6.5
4.5tM–5
3.5tM–5
1.5tM–11.5
4.5tM–6.5
14
tM–9
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
MADL0–MADL7
Refresh
Address
16
15
18
Address
19
MRAS
73a
73b
MCAS
73c
73d
MREF
Figure 15. Memory-Bus DRAM-Refresh Cycle
XMATCH and XFAIL timing (see Figure 16)
t_M is the cycle time of one-eighth of a local-memory cycle (31.25 ns minimum for a 4-MHz local bus or 20.83 ns
minimum for a 6-MHz local bus).
NO.
127 Delay time, status bit 7 high to XMATCH and XFAIL recognized
128 Pulse duration, XMATCH or XFAIL high
4-MHz local bus
6-MHz local bus
MIN MAX UNIT
7tM
ns
50
ns
30
MADH7
Status
Bit 7
127
128
XMATCH
XFAIL
Figure 16. XMATCH and XFAIL
48
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