TI380C30A Datasheet, PDF (28/81 Pages) Texas Instruments – INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE

TI380C30A
INTEGRATED TOKEN-RING COMMPROCESSOR
AND PHYSICAL-LAYER INTERFACE
SPWS034 – MARCH 1998
Table 5. SIFACL Bit Definitions
BIT
NAME
FUNCTION
Value on TEST0 and TEST2 pins. These bits are read-only bits and reflect the value on the corresponding device
pins. This allows the host software (S/W) to determine speed configuration. If the network speed and type are
software-configurable, these bits are used to determine the configurations that are supported by the network
TEST0
hardware.
0–2
TEST1
TEST2
TEST0 TEST1 TEST2 Description
L
NC
H
16-Mbit/s token ring
H
NC
H
4-Mbit/s token ring
X
X
L
Reserved
3
Reserved Read data should be 0.
Software-hold acknowledge. Allows the function of SHLDA/SBGR to be emulated from software control for
pseudo-DMA mode.
PSDMAEN SWHLDA SWHRQ Result
4
SWHLDA
0†
1†
X
0
X
SWHLDA value in the SIFACL register cannot be set to a 1.
0
No pseudo-DMA request pending
1†
0
1
Indicates a pseudo-DMA request interrupt
1†
1
X
Pseudo-DMA process in progress
† _{The value on SHLDA/SBGR is ignored.}
Current SDDIR signal value. Contains the current value of the pseudo-DMA direction. This enables the host to easily
determine the direction of DMA transfers, which allows system DMA to be controlled by system software.
5
SWDDIR
0 = Pseudo DMA from host system to TI380C30A
1 = Pseudo DMA from TI380C30A to host system
Current SHRQ signal value. Contains the current value on SHRQ/SBRQ when in Intel mode and the inverse of the
value on SHRQ/SBRQ in Motorola mode. This enables the host to easily determine if a pseudo-DMA transfer is
requested.
6
SWHRQ
Intel Mode (SI/M = H)
Motorola Mode (SI/M = L)
0 = System bus not requested
1 = System bus not requested
1 = System bus requested
0 = System bus requested
Pseudo-system-DMA enable. Enables pseudo-DMA operation.
7
PSDMAEN ^{0 = Normal bus-master DMA operation is possible.}
1 = Pseudo-DMA operation selected. Operations dependent on the values of the SWHLDA and SWHRQ bits in the
SIFACL register.
Adapter reset. ARESET is a hardware reset of the TI380C30A. This bit has the same effect as SRESET except that
the DIO interface to the SIFACL register is maintained. This bit is set to 1 if a clock failure is detected (OSCIN, PXTAL,
8
ARESET ^{RCLK, or SBCLK not valid).}
0 = TI380C30A operates normally.
1 = TI380C30A is held in the reset condition.
Communications processor halt. Controls the TI380C30A processor access to the internal TI380C30A buses. This
prevents the TI380C30A from executing instructions before the microcode is downloaded.
9
CPHALT
0 = TI380C30A processor can access the internal TI380C30A buses.
1 = TI380C30A processor cannot access the internal-adapter buses.
Bootstrap CP code. Indicates whether the memory in chapters 0 and 31 of the local-memory space is RAM or
ROM/PROM/EPROM. This bit controls the operation of MCAS and MROMEN.
10
BOOT
0 = ROM/PROM/EPROM memory in chapters 0 and 31
1 = RAM memory in chapters 0 and 31
Local bus priority. Controls the priority levels of devices on the local bus.
0 = No external devices (such as TI380FPA) are used with the TI380C30A.
11
LBP
1 = An external device (such as TI380FPA) is used with the TI380C30A. This allows the external bus master to
operate at the necessary priority on the local bus.
If the system uses the TMS380SRA only, the bit must be set to 0. If the system uses both the TMS380SRA and the
TI380FPA, the bit must be set to 1.
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