TI380C30A Datasheet, PDF (56/81 Pages) Texas Instruments – INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE

TI380C30A
INTEGRATED TOKEN-RING COMMPROCESSOR
AND PHYSICAL-LAYER INTERFACE
SPWS034 – MARCH 1998
SCS
SRSX
SRS0–SRS2,
SBHE
Only SCS needs to be inactive.
All others are don’t care.
SIACK
272a
273a
SWR
272a
273a
SRD
272a
SDDIR
High
SDBEN
282R
273a
279
283R
276
282a
275
255
SRDY†
Hi-Z
Hi-Z
259
SADH0–SADH7
SADL0–SADL7
SPH
Hi-Z
SPL‡
260 261a
Output Data Valid
† _{SRDY is an active-low bus-ready signal. It must be asserted before data output.}
‡ _{In 8-bit 80x8x-mode DIO writes, the value placed on SADH0–SADH7 is a don’t care.}
261
Hi-Z
Figure 22. 80x8x Interrupt-Acknowledge Cycle – Second SIACK Pulse
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