TI380C30A Datasheet, PDF (74/81 Pages) Texas Instruments – INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE

TI380C30A
INTEGRATED TOKEN-RING COMMPROCESSOR
AND PHYSICAL-LAYER INTERFACE
SPWS034 – MARCH 1998
68xxx-mode DMA write cycle (see Figure 33)
NO.
208a
208b
Setup time, asynchronous input SDTACK before SBCLK no longer
high to assure recognition on this cycle
Hold time, asynchronous input SDTACK after SBCLK low to assure
recognition on this cycle
209 Pulse duration, SAS, SUDS, and SLDS high
211 Delay time, SBCLK high in T2 cycle to SUDS and SLDS active
211a Delay time, output data valid to SUDS and SLDS no longer high
212 Delay time, SBCLK low to address valid
216 Delay time, SBCLK high to SALE or SXAL high
216a Hold time, SALE or SXAL low after SUDS and SAS high
217
Delay time, SBCLK high to SXAL low in the TX cycle or SALE low in
the T1 cycle
218 Hold time, address valid after SALE, SXAL low
219 Delay time, SBCLK low in T2 cycle to output data and parity valid
221 Hold time, output data, parity valid after SUDS and SLDS high
222 Delay time, SBCLK high to SAS low
223W Delay time, SBCLK low to SUDS, SLDS, and SAS high
225W Delay time, SBCLK high in T4 cycle to SDBEN high
225WH Hold time, SDBEN low after SUDS and SLDS high
233 Setup time, address valid before SALE or SXAL no longer high
233a Setup time, address valid before SAS no longer high
237W Delay time, SBCLK high in T1 cycle to SDBEN low
25-MHZ OPERATION 33-MHZ OPERATION
UNIT
MIN MAX
MIN MAX
10
10
ns
10
tc(SCK)+
tw(SCKL)–18
tw(SCKL)–15
0
0
5
tc(SCK)–12
0
tc(SCK)/2–7
10
tw(SCKL)–15
10
tc(SCK)+
tw(SCKL)–18
25
tw(SCKL)–15
20
20
0
25
0
5
29
tc(SCK)–12
20
16
0
16
tc(SCK)/2–7
10
tw(SCKL)–15
16
ns
ns
25 ns
ns
20 ns
20 ns
ns
25 ns
ns
29 ns
ns
15 ns
11 ns
11 ns
ns
ns
ns
11 ns
74
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