TI380C30A Datasheet, PDF (15/81 Pages) Texas Instruments – INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE

TI380C30A
INTEGRATED TOKEN-RING COMMPROCESSOR
AND PHYSICAL-LAYER INTERFACE
SPWS034 – MARCH 1998
Terminal Functions (Continued)
TERMINAL
NAME
NO.
I/O/E†
DESCRIPTION
S8/SHALT
69
S8 is used for system 8-/16-bit bus select. S8 selects the bus width used for
Intel
mode
communications through the system interface. On the rising edge of SRESET, the
TI380C30A latches the DMA bus width; otherwise, the value on S8 dynamically
selects the DIO bus width.
H = Selects 8-bit mode (see Note 1)
L = Selects 16-bit mode
I
SHALT is used for system halt/bus error retry. If SHALT is asserted along with bus
error (SBERR), the adapter retries the last DMA cycle. This is the rerun operation as
Motorola
mode
defined in the 68xxx specification. The BERETRY counter is not decremented by
SBERR when SHALT is asserted (see section 3.4.5.3 of the TMS380
Second-Generation Token-Ring User’s Guide, literature number SPWU005, for
more information).
TCLK
TMS
TDI
TDO
7 I (see Note 1)
8 I (see Note 1) Test ports used during the production test of the device. TCLK, TMS, TDI, and TDO must be left
165 I (see Note 1) unconnected.
164
O
Network select inputs. TEST0–TEST2 are used to select the network speed and type to be used
by the TI380C30A. These inputs should be changed only during adapter reset. Connect TEST2 to
TEST0
116
I
VDDL.
TEST1
115
I
TEST2
114
I
TEST0 TEST1 TEST2
Description
L
NC
H
16-Mbit/s token ring
H
NC
H
4-Mbit/s token ring
X
X
L
Reserved
TEST3
TEST4
TEST5
113
112
111
I
I
I
Test inputs. TEST3–TEST5 should be left unconnected (see Note 1). Module-in-place test mode
is achieved by tying TEST3 and TEST4 to ground. In this mode, all TI380C30A outputs are in the
high-impedance state. Internal pullups on all TI380C30A inputs are disabled (except
TEST3–TEST5).
TRST
Test-port reset. TRST should be tied to ground for normal operation of the TI380C30A (see Note 1).
9
I
H = Reserved
L = Test ports forced to an idle state
VDD
14
29
45
87
—
Positive-supply voltage for commprocessor output buffers. All VDD pins must be attached to the
common-system power-supply plane.
103
119
VDDA1
148
—
Positive-supply voltage for receiver circuits
VDDA2
129
—
Positive-supply voltage for data recovery PLL
VDDA3
123
Positive-supply voltage for the current-bias generator
VDDD
157
—
Positive-supply voltage for physical layer output buffers
VDDL
13
47
71
—
Positive-supply voltage for commprocessor digital logic. All VDDL pins must be attached to the
common-system power-supply plane.
VDDL1
134
146
—
Positive-supply voltage for physical layer digital logic. All VDDL pins must be attached to the
common-system power-supply plane.
VDDO
133
—
Positive-supply voltage for XTAL oscillator
VDDP
138
—
Positive-supply voltage for phantom drive
VDDX
145
—
Positive-supply voltage for transmit output
† _{I = input, O = output, E = provides external-component connection to the internal circuitry for tuning}
NOTE 1. Terminal has an internal pullup device to maintain a high-voltage level when left unconnected (no etch).
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