TI380C30A Datasheet, PDF (49/81 Pages) Texas Instruments – INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE

TI380C30A
INTEGRATED TOKEN-RING COMMPROCESSOR
AND PHYSICAL-LAYER INTERFACE
SPWS034 – MARCH 1998
token-ring timing
ring interface (see Figure 17)
NO.
153 Period of RCLK (see Note 23)
4 Mbit/s
16 Mbit/s
154L Pulse duration, RCLK low
4 Mbit/s nominal: 62.5 ns
16 Mbit/s nominal: 15.625 ns
154H Pulse duration, RCLK high
4 Mbit/s nominal: 62.5 ns
16 Mbit/s nominal: 15.625 ns
155 Setup time, RCVR valid before rising edge (1.8 V) of RCLK at 16 Mbit/s
156 Hold time, RCVR valid after rising edge (1.8 V) of RCLK at 16 Mbit/s
158L Pulse duration, ring-baud clock low
4 Mbit/s
16 Mbit/s
158H Pulse duration, ring-baud clock high
4 Mbit/s
16 Mbit/s
165 Period of OSCOUT and PXTAL (see Note 23)
4 Mbit/s
16 Mbit/s (for PXTALIN only)
Tolerance of PXTAL input frequency (see Note 23)
NOTE 23: This parameter is not tested but is required by the IEEE Std 802.5 specification.
MIN TYP MAX
125
31.25
46
15
35
8
10
1
40
8
40
8
125
31.25
±0.01
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
%
153
154H
RCLK
154L
156
155
RCVR ^{ÌÌÌÌÌÌÌÌÌÌÌÌ} Valid
ÌÌÌÌÌÌÌÌÌÌ
158H
158L
165
OSCOUT
PXTAL
1.5 V
Figure 17. Ring Interface
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