TI380C30A Datasheet, PDF (23/81 Pages) Texas Instruments – INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE

TI380C30A
INTEGRATED TOKEN-RING COMMPROCESSOR
AND PHYSICAL-LAYER INTERFACE
SPWS034 – MARCH 1998
frequency acquisition and REDY
Unlike its predecessors, the TMS3805x family, the data-recovery PLL of the TI380C30A physical layer does not
require constant frequency monitoring; neither is it necessary to recenter its frequency by way of the FRAQ
control line. When the commprocessor asserts FRAQ, it initiates a reset of the clock-recovery PLL. The REDY
signal is deasserted for the duration of this action and reasserted low when it is complete (a maximum of 3 µs
later). This low-going transition of REDY is required by the commprocessor following the setting of FRAQ high
to indicate to the PH that any frequency error that it could have detected has been corrected. REDY is not
asserted if no incoming transitions are detected by the rate-error function.
rate error (RATER) function
RATER provides an indication that incoming data transitions are present on the RCV+/RCV– pair, but that the
rate of transitions is outside the range that is expected for the ring speed selected by S4/16. RATER is not
asserted low if no incoming transitions are present. In wrap mode, the rate-error function monitors the transitions
on the DRVR+/DRVR– pair.
The rate-error function interprets 16 or more transitions in a 1.5-ms period as valid 16-Mbit/s data. It interprets
15 or fewer transitions in a 1.5-ms period as 4-Mbit/s data. One transition or less in a 1.5-ms period is interpreted
as no incoming transitions, in which case, RATER and REDY are not asserted low.
power-down control
The TI380C30A PHY can be disabled by the PWRDN signal. If PWRDN is taken low, all outputs of the PHY are
in the high-impedance state and all internal logic is powered down, bringing power consumption to a very low
level. Upon taking PWRDN high, the device resets and initializes itself. This process could take up to 2 ms and
care should be taken to ensure that the system does not require stable clocks during this period.
user-accessible hardware registers and TI380C30A-internal pointers
Table 3 and Table 4 show how to access internal data by way of pointers and how to address the registers in
the host interface. The SIF adapter-control (SIFACL) register, which directly controls device operation, is
described in detail. The adapter-internal pointers table is defined only after TI380C30A initialization and until
the OPEN command is issued. These pointers are defined by the TI380C30A software (microcode), and this
table describes the release 2.x software.
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