TI380C30A Datasheet, PDF (29/81 Pages) Texas Instruments – INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE

TI380C30A
INTEGRATED TOKEN-RING COMMPROCESSOR
AND PHYSICAL-LAYER INTERFACE
SPWS034 – MARCH 1998
Table 5. SIFACL Bit Definitions (Continued)
BIT
NAME
FUNCTION
System-interrupt enable. Allows the host processor to enable or disable system-interrupt requests from the
TI380C30A. The system-interrupt request from the TI380C30A is on SINTR/SIRQ. The following equation shows
how SINTR/SIRQ is driven:
12
13
14–15
SINTEN
PEN
NSELOUT0
NSELOUT1
SINTR/SIRQ = (PSDMAEN * SWHRQ * !SWHLDA) + (SINTEN * SYSTEM_INTERRUPT)
Results of the states are:
System Interrupt
PSDMAEN SWHRQ SWHLDA SINTEN
(SIFTS
Register) Result
1†
1
1
X
1†
1
0
X
X
Pseudo DMA is active.
X
TI380C30A generates a system interrupt for a
1†
0
0
X
pseudo DMA.
X
Not a pseudo-DMA interrupt
X
X
X
1
0
X
X
1
1
TI380C30A generates a system interrupt.
0
TI380C30A does not generate a system
interrupt.
0
X
X
0
X
TI380C30A cannot generate a system interrupt.
† _{The value on SHLDA/SBGR is ignored.}
Parity enable. Determines whether data transfers within the TI380C30A are checked for parity.
0 = Data transfers are not checked for parity.
1 = Data transfers are checked for correct odd parity.
Network-selection outputs. Values control NSELOUT0 and NSELOUT1. These bits can be modified only while the
ARESET bit is set.
These bits can be used to software-configure a TI380C30A: NSELOUT0 should be connected to TEST0 (TEST1
should be left unconnected and TEST2 should be tied high). NSELOUT0 and NSELOUT1 are used to select network
speed as follows:
NSELOUT0
0
0
1
1
NSELOUT1
0
1
0
1
Selection
Reserved
16-Mbit/s token ring
Reserved
4-Mbit/s token ring
At power up, these bits are set corresponding to 16-Mbit/s token ring (NSELOUT1 = 1, NSELOUT0 = 0). New values
are saved only if written in the same cycle that the ARESET bit is cleared.
SIFACL control for pseudo-DMA operation
Pseudo-DMA operation is software-controlled by using five bits in the SIFACL register. The logic model for the
SIFACL control of pseudo-DMA operation is shown in Figure 5.
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