TI380C30A Datasheet, PDF (69/81 Pages) Texas Instruments – INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE

SCS
SRSX
SRS0
SRS1
SBHE
TI380C30A
INTEGRATED TOKEN-RING COMMPROCESSOR
AND PHYSICAL-LAYER INTERFACE
SPWS034 – MARCH 1998
Only SCS needs to be Inactive.
All others are don’t care.
267
SIACK
272a
SRNW
286
273a
SLDS
SDDIR
High
282R
286
279
283R
SDBEN
276
282a
275
255
SDTACK†
Hi-Z
Hi-Z
259
SADH0–SADH7
SADL0–SADL7
Hi-Z
SPH
SPL‡
261
260 261a
Output Data Valid
Hi-Z
† _{SDTACK is an active-low bus ready signal. It must be asserted before data output.}
‡ _{Internal logic drives SDTACK high and verifies that it has reached a valid-high level before making it a 3-state signal.}
Figure 30. 68xxx Interrupt-Acknowledge Cycle
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69