TI380C30A Datasheet, PDF (66/81 Pages) Texas Instruments – INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE

TI380C30A
INTEGRATED TOKEN-RING COMMPROCESSOR
AND PHYSICAL-LAYER INTERFACE
SPWS034 – MARCH 1998
68xxx DIO write cycle (see Figure 29)123456789101112131415161718192021222324
25-MHZ OPERATION 33-MHZ OPERATION
NO.
UNIT
MIN
MAX
MIN
MAX
255 Delay time, SDTACK low to either SCS, SUDS, or SLDS high
15
15
ns
262 Setup time, write data valid before SUDS or SLDS no longer low
15
15
ns
263 Hold time, write data valid after SUDS or SLDS high
15
15
ns
267†
Setup time, register address before SUDS or SLDS no longer high
(see Note 25)
15
15
ns
268
Hold time, register address valid after SUDS or SLDS no longer low
(see Note 26)
0
0
ns
272
Setup time, SRNW before SUDS or SLDS no longer high
(see Note 25)
12
12
ns
272a
Setup time, inactive SUDS or SLDS high to active data strobe no
longer high
tc(SCK)
tc(SCK)
ns
273 Hold time, SRNW after SUDS or SLDS high
0
0
ns
273a
275
Hold time, inactive SUDS or SLDS high after active data strobe high
Delay time, SCS, SUDS, or SLDS high to SDTACK high
(see Note 25)
tc(SCK)
0
tc(SCK)
25
0
ns
25 ns
276
Delay time, SDTACK low in the first DIO access to the SIF register
to SDTACK low in the immediately following access to the SIF
4000
4000 ns
279‡
Delay time, SUDS or SLDS high to SDTACK in the high-impedance
state
0
tc(SCK)
0
tc(SCK) ns
280
282b
Delay time, SUDS or SLDS low to SDDIR low (see Note 25)
Delay time, SDBEN low to SDTACK low
(see TMS380 Second Generation
Token-Ring User’s Guide, literaure
number SPWU005, subsection 3.4.1.1.1)
If SIF register is ready
(no waiting required)
If SIF register is not
ready (waiting required)
0 tc(SCK)/2+4
0 tc(SCK)/2+4
0
4000
0 tc(SCK)/2+4 ns
0 tc(SCK)/2+4
ns
0
4000
282W Delay time, SDDIR low to SDBEN low
0 tc(SCK)/2+4
0 tc(SCK)/2+4 ns
283W Delay time, SUDS or SLDS high to SDBEN no longer low
0 tc(SCK)/2+4
0 tc(SCK)/2+4 ns
286
Pulse duration, SUDS or SLDS high between DIO accesses
(see Note 25)
tc(SCK)
tc(SCK)
ns
† _{It is the later of SRD and SWR or SCS low that indicates the start of the cycle.}
‡ _{This specification is provided as an aid to board design.}
NOTES: 25. The inactive chip-select is SIACK in DIO-read and DIO-write cycles; SCS is the inactive chip-select in interrupt-acknowledge cycles.
26. In 80x8x mode, SRAS can be used to strobe the values of SBHE, SRSX, SRS0–SRS2, and SCS. When used to do so, SRAS must
meet parameter 266a, and SBHE, SRS0–SRS2, and SCS must meet parameter 264. If SRAS is strapped high, parameters 266a
and 264 are irrelevant and parameter 268 must be met.
66
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265