TI380C30A Datasheet, PDF (73/81 Pages) Texas Instruments – INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE

T4
SBCLK
SAS†
SUDS
SLDS
SRNW
SXAL
High
216
TI380C30A
INTEGRATED TOKEN-RING COMMPROCESSOR
AND PHYSICAL-LAYER INTERFACE
SPWS034 – MARCH 1998
TWAIT
TX
T1
T2
V
T3
T4
T1
S1 S2 S3
S4 S5 S6 S7
222
209
210
223R
218
217
209
217
SALE
SADL0–SADH7
SADH0–SADL7
SPH
SPL
SDTACK§^¶
216
218
216a
212
233
212
233a
233
Extended Address
214 205
Address
208a
247‡
229
206
207a
Data In
Hi-Z
207b
208b
SDDIR
Low
237R
225R
SDBEN†
† _{On a read cycle, the read strobe remains active until the internal sample of incoming data is completed. Input data may be removed when}
either the read strobe or SDBEN becomes inactive.
‡ _{If parameter 208a is not met, then valid data must be present before SDTACK goes low.}
§ _{Motorola-style bus slaves hold SDTACK active until the bus master deasserts SAS.}
¶ _{All VSS pins should be routed to minimize inductance to system ground.}
Figure 32. 68xxx-Mode DMA Read Cycle
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73