TI380C30A Datasheet, PDF (46/81 Pages) Texas Instruments – INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE

TI380C30A
INTEGRATED TOKEN-RING COMMPROCESSOR
AND PHYSICAL-LAYER INTERFACE
SPWS034 – MARCH 1998
memory-bus timing (continued)
t_M is the cycle time of one-eighth of a local-memory cycle (31.25 ns minimum for a 4-MHz local bus or 20.83 ns
minimum for a 6-MHz local bus).
memory-bus write cycle (see Figure 14)
NO.
58 Setup time, MW low before MRAS no longer low
60 Setup time, MW low before MCAS no longer low
63 Setup time, valid data/parity before MW no longer high
64 Pulse duration, MW low
65 Hold time, data/parity out valid after MW high
66 Setup time, address valid on MAX0, MAX2, and MROMEN before MW no longer low
67 Hold time, MRAS low to MW no longer low
69 Hold time, MCAS low to MW no longer low
70 Setup time, MBEN low before MW no longer high
71 Hold time, MBEN low after MW high
72 Setup time, MDDIR high before MBEN no longer high
73 Hold time, MDDIR high after MBEN high
MIN
tM
1.5tM–6.5
5.1
2.5tM–9
0.5tM–10.5
7tM–11.5
5.5tM–9
4tM–11.5
1.5tM–13.5
0.5tM–6.5
2tM–9
1.5tM–12
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
46
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