TI380C30A Datasheet, PDF (78/81 Pages) Texas Instruments – INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE

TI380C30A
INTEGRATED TOKEN-RING COMMPROCESSOR
AND PHYSICAL-LAYER INTERFACE
SPWS034 – MARCH 1998
T1
T(W or 2)
T3
T4
TH
T1
SBCLK
SDTACK
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
SBERR
SHALT
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
Figure 36. 68xxx-Mode Bus Halt and Retry, Normal Completion With Delayed Start^†
† _{Only the relative placement of the edges to SBCLK falling edge is shown. Actual signal edge placement can vary from waveforms shown.}
T1
SBCLK
SDTACK
T2
T3
T4
THB
THE
T1
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
SBERR
SHALT
ÌÌÌÌÌÌÌÌÌÌÌÌ
SOWN
Figure 37. 68xxx-Mode Bus Halt and Retry, Rerun Cycle With Delayed Start^†
† _{Only the relative placement of the edges to SBCLK falling edge is shown. Actual signal edge placement can vary from waveforms shown.}
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