TI380C30A Datasheet, PDF (11/81 Pages) Texas Instruments – INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE

TI380C30A
INTEGRATED TOKEN-RING COMMPROCESSOR
AND PHYSICAL-LAYER INTERFACE
SPWS034 – MARCH 1998
Terminal Functions (Continued)
TERMINAL
NAME
NO.
I/O/E†
DESCRIPTION
PLL ready. REDY is normally asserted (active) low. It is cleared following the assertion of FRAQ and
reasserted after the data recovery PLL has been reinitialized.
REDY
124
O
H = Received data not valid (or signal not present)
L = Received data valid
The signal loss indication is in lieu of ring status (SSB_CMD = 0X0001, ring_status bit 0) signal loss
indication.
RES
137
—
Reserved. RES should be left unconnected.
SADH0
SADH1
SADH2
SADH3
SADH4
SADH5
SADH6
SADH7
110
109
System address/data bus – high byte (see Note 1). These lines make up the most significant byte of each
108
address word (32-bit address bus) and data word (16-bit data bus). The most significant bit (MSB) is
107
106
105
101
I/O
SADH0, and the least significant bit (LSB) is SADH7.
Address multiplexing: Bits 31–24 and bits 15–8‡
Data multiplexing: Bits 15–8‡
100
SADL0
SADL1
SADL2
SADL3
SADL4
SADL5
SADL6
SADL7
91
90
System address/data bus – low byte (see Note 1). These lines make up the least significant byte of each
89
address word (32-bit address bus) and data word (16-bit data bus). The most significant bit is SADL0,
86
85
84
83
I/O ^{and the least significant bit is SADL7.}
Address multiplexing: Bits 23–16 and bits 7–0‡
Data multiplexing: Bits 7–0‡
82
SALE
System address-latch enable. SALE is the enable pulse used to externally latch the 16 LSBs of the
80
O
address from the SADH and SADL buses at the start of the DMA cycle. Systems that implement address
parity can also externally latch the parity bits (SPH and SPL) for the latched address.
SBBSY
System bus busy. The TI380C30A samples the value on SBBSY during arbitration (see Note 1). The
sample has one of two values:
68
I
H = Not busy. The TI380C30A can become bus master if the grant condition is met.
L = Busy. The TI380C30A cannot become bus master.
SBCLK
81
I
System bus clock. The TI380C30A requires the external clock to synchronize its bus timings for all DMA
transfers. Valid frequencies are 2 MHz–33 MHz.
SBHE/SRNW ⁹⁴
SBHE is used for system-byte-high enable. SBHE is a 3-state output driven during DMA;
Intel™
it is an input at all other times.
mode
H = System byte high not enabled (see Note 1)
L = System byte high enabled
I/O
SRNW is used for system read, not write. SRNW serves as a control signal to indicate a
Motorola™ ^{read or write cycle.}
mode
H = Read cycle (see Note 1)
L = Write cycle
SBRLS
System-bus release. SBRLS indicates to the TI380C30A that a higher-priority device requires the system
bus. The value on SBRLS is ignored when the TI380C30A is not performing DMA. SBRLS is internally
synchronized to SBCLK.
67
I
H = The TI380C30A can hold onto the system bus (see Note 1)
L = The TI380C30A should release the system bus upon completion of current DMA cycle. If the DMA
transfer is not yet complete, the SIF rearbitrates for the system bus.
† _{I = input, O = output, E = provides external-component connection to the internal circuitry for tuning}
‡ _{Typical bit ordering for Intel™ and Motorola™ processor buses}
NOTE 1. Terminal has an internal pullup device to maintain a high-voltage level when left unconnected (no etch).
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