TI380C30A Datasheet, PDF (6/81 Pages) Texas Instruments – INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE

TI380C30A
INTEGRATED TOKEN-RING COMMPROCESSOR
AND PHYSICAL-LAYER INTERFACE
SPWS034 – MARCH 1998
functional block diagram
SADH0
SADH7
SADL0
SADL7
SPH
SPL
SBRLS
SINTR/SIRQ
SDDIR
SDBEN
SALE
SXAL
SOWN
SIACK
SBCLK
SRD/SUDS
SWR/SLDS
SRDY/SDTACK
SI/M
SHLDA/SBGR
SBHE/SRNW
SRAS/SAS
S8/SHALT
SRESET
SRS0
SRS1
SRS2/SBERR
SCS
SRSX
SHRQ/SBRQ
SBBSY
BTSTRP
PRTYEN
NSELOUT0
NSELOUT1
SIF
• DIO Control
• Bus Control
• DMA Control
MIF
• DRAM Refresh
• Local-Bus
Arbitrator
• Local-Bus
Control
• Local
Parity-Check/
Generator
CG
Communications
Processor
ASF
• Interrupts
• Test Function
RCLK†
REDY†
WFLT†
RCVR†
PXTAL†
OSC32
TCLK
TMS
TRST
ATEST
XT1
XT2
PHOUTA
PHOUTB
EQ–
EQ+
Token-Ring PH
PHY Interface
Test Port
PHY
= Analog Signal
† _{Signals are provided for test-monitoring purposes.}
MADH0
MADH7
MADL0
MADL7
MRAS
MCAS
MAXPH
MAXPL
MW
MOE
MDDIR
MAL
MAX0
MAX2
MRESET
MROMEN
MBEN
MBRQ
MBGR
MACS
MBIAEN
MREF
OSCIN
OSCOUT
MBCLK1
MBCLK2
SYNCIN
CLKDIV
NMI
EXTINT0
EXTINT3
TEST0
TEST5
XMATCH
XFAIL
FRAQ†
NSRT†
WRAP†
DRVR+†
DRVR–†
XMT+
XMT–
RCV+
RCV–
PWRDN
S4/16
NABL
RATER
TDO
TDI
6
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