TI380C30A Datasheet, PDF (50/81 Pages) Texas Instruments – INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE

TI380C30A
INTEGRATED TOKEN-RING COMMPROCESSOR
AND PHYSICAL-LAYER INTERFACE
SPWS034 – MARCH 1998
transmitter timing (see Figure 18)
NO.
MIN MAX UNIT
159 tsk(DR)
Delay time, DRVR+ rising edge (1.8 V) to DRVR– falling edge (1 V) or
DRVR+ falling edge (1 V) to DRVR– rising edge (1.8 V)
±2 ns
160 td(DR)H†
161 td(DR)L†
162 td(DRN)H†
163 t(DRN)L†
164
DRVR+/DRVR–
asymmetry
Delay time, RCLK (or PXTAL) falling edge (1 V) to DRVR+ rising edge (1.8 V)
Delay time, RCLK (or PXTAL) falling edge (1 V) to DRVR+ falling edge (1 V)
Delay time, RCLK (or PXTAL) falling edge (1 V) to DRVR– falling edge (1 V)
Delay time, RCLK (or PXTAL) falling edge (1 V) to DRVR– rising edge (1.8 V)
) ) t_d(DR)L
t_d(DRN)H
2
–
t_d(DR)H
t_d(DRN)L
2
See Note 24
ns
See Note 24
ns
See Note 24
ns
See Note 24
ns
±1.5 ns
† _{When in active-monitor mode, the clock source is PXTAL; otherwise, the clock source is either RCLK or PXTAL.}
NOTE 24: This parameter is not tested to a minimum or a maximum, but is measured and used as a component required for parameter 164.
RCLK or PXTAL
2.6 V
1.5 V
0.6 V
DRVR+
DRVR–
160
159
162
2.4 V
1.5 V
0.6 V
161
159
163
2.4 V
1.5 V
0.6 V
Figure 18. Skew and Asymmetry From RCLK or PXTAL to DRVR+ and DRVR–
50
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