TI380C30A Datasheet, PDF (68/81 Pages) Texas Instruments – INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE

TI380C30A
INTEGRATED TOKEN-RING COMMPROCESSOR
AND PHYSICAL-LAYER INTERFACE
SPWS034 – MARCH 1998
68xxx interrupt-acknowledge-cycle timing (see Figure 30)
25-MHZ OPERATION 33-MHZ OPERATION
NO.
UNIT
MIN
MAX
MIN
MAX
255 Delay time, SDTACK low to either SCS or SUDS, or SIACK high
15
15
ns
259†
Hold time, SAD in the high-impedance state after SIACK no longer
high (see Note 25)
0
0
ns
260 Setup time, output data valid before SDTACK no longer high
0
0
ns
261†
Delay time, SIACK high to SAD in the high-impedance state
(see Note 25)
35
35 ns
261a
Hold time, output data valid after SCS or SIACK no longer low
(see Note 25)
0
0
ns
267‡
Setup time, register address before SIACK no longer high
(see Note 25)
15
15
ns
272a
273a
275
Setup time, inactive high SIACK to active data strobe no longer high
Hold time, inactive SRNW high after active data strobe high
Delay time, SCS or SRNW high to SDTACK high (see Note 25)
tc(SCK)
tc(SCK)
0
tc(SCK)
tc(SCK)
25
0
ns
ns
25 ns
276
279†
282a
282R
Delay time, SDTACK low in the first DIO access to the SIF register
to SDTACK low in the immediately following access to the SIF
Delay time, SIACK high to SDTACK in the high-impedance state
Delay time, SDBEN low to SDTACK low in a read cycle
Delay time, SIACK low to SDBEN low (see TMS380 Second
Generation Token-Ring User’s Guide, literature number SPWU005,
subsection 3.4.1.1.1), provided the previous cycle completed
0
4000
0
tc(SCK)
0 tc(SCK)/2+4
0 tc(SCK)+3
0
4000 ns
0
tc(SCK) ns
0 tc(SCK)/2+4 ns
0 tc(SCK)+3 ns
283R Delay time, SIACK high to SDBEN high (see Note 25)
0 tc(SCK)/2+4
0 tc(SCK)/2+4 ns
286 Pulse duration, SIACK high between DIO accesses (see Note 25)
tc(SCK)
tc(SCK)
ns
† _{This specification is provided as an aid to board design.}
‡ _{It is the later of SRD and SRD or SCS low that indicates the start of the cycle.}
NOTE 25. The inactive chip-select is SIACK in DIO-read and DIO-write cycles; SCS is the inactive chip-select in interrupt-acknowledge cycles.
68
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