TI380C30A Datasheet, PDF (72/81 Pages) Texas Instruments – INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE

TI380C30A
INTEGRATED TOKEN-RING COMMPROCESSOR
AND PHYSICAL-LAYER INTERFACE
SPWS034 – MARCH 1998
68xxx-mode DMA timing
68xxx-mode DMA read cycle (see Figure 32)
25-MHZ OPERATION 33-MHZ OPERATION
NO.
MIN MAX
MIN MAX
205 Setup time, input data valid before SBCLK in T3 cycle no longer high
10
10
206
Hold time, input data valid after SBCLK low in T4 cycle if parameters
207a and 207b not met
10
10
207a Hold time, input data valid after data strobe no longer low
0
0
207b Hold time, input data valid after SDBEN no longer low
0
0
208a
Setup time, asynchronous input SDTACK before SBCLK no longer high
to assure recognition on this cycle
10
10
208b
Hold time, asynchronous input SDTACK after SBCLK low to assure
recognition on this cycle
10
10
209 Pulse duration, SAS, SUDS, and SLDS high
210 Delay time, SBCLK high in T2 cycle to SUDS and SLDS active
tc(SCK)+
tw(SCKL)–18
tc(SCK)+
tw(SCKL)–18
16
11
212 Delay time, SBCLK low to address valid
20
20
214 Delay time, SBCLK low in T2 cycle to SAD high impedance
20
15
216 Delay time, SBCLK high to SALE or SXAL high
20
20
216a Hold time, SALE or SXAL low after SUDS and SAS high
0
0
217
Delay time, SBCLK high to SXAL low in the TX cycle or
SALE low in the T1 cycle
0
25
0
25
218 Hold time, address valid after SALE, SXAL low
5
5
222 Delay time, SBCLK high to SAS low
20
15
223R
Delay time, SBCLK low in T4 cycle to SUDS, SLDS, and SAS high
(see Note 27)
0
16
0
11
225R Delay time, SBCLK low in T4 cycle to SDBEN high
16
11
229
Hold time, SAD in the high-impedance state
after SBCLK low in T4 cycle
0
0
233 Setup time, address valid before SALE or SXAL no longer high
10
10
233a Setup time, address valid before SAS no longer high
237R Delay time, SBCLK high in the T2 cycle to SDBEN low
tw(SCKL)–15
tw(SCKL)–15
16
11
247 Setup time, data valid before SDTACK low if parameter 208a not met
0
0
NOTE 27: While the system-interface DMA controls are active (that is, SOWN is asserted), SCS is disabled.
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
72
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