TI380C30A Datasheet, PDF (58/81 Pages) Texas Instruments – INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE

TI380C30A
INTEGRATED TOKEN-RING COMMPROCESSOR
AND PHYSICAL-LAYER INTERFACE
SPWS034 – MARCH 1998
80x8x-mode DMA timing
80x8x-mode DMA read cycle (see Figure 24)
25-MHZ
33-MHZ
NO.
OPERATION
OPERATION
MIN MAX
MIN MAX
205
Setup time, SADL0–SADL7, SADH0–SADH7, SPH, and
SPL valid before SBCLK in T3 cycle no longer high
10
10
Hold time, SADL0–SADL7, SADH0–SADH7, SPH, and SPL valid after
206 _{SBCLK low in T4 cycle if parameters 207a and 207b not met}
10
10
207a
Hold time, SADL0–SADL7, SADH0–SADH7, SPH, and
SPL valid after SRD high
0
0
207b
Hold time, SADL0–SADL7, SADH0–SADH7, SPH, and
SPL valid after SDBEN no longer low
0
0
208a
Setup time, asynchronous signal SRDY before SBCLK no longer high to
assure recognition on this cycle
10
10
Hold time, asynchronous signal SRDY after SBCLK low to assure
208b _{recognition on this cycle}
10
10
212 Delay time, SBCLK low to address valid
20
20
Delay time, SBCLK low in T1 cycle to SADH0–SADH7, SADL0–SADL7,
214 _{SPH, and SPL in the high-impedance state}
20
15
216 Delay time, SBCLK high to SALE or SXAL high
20
20
216a Hold time, SALE or SXAL low after SRD high
0
0
217
Delay time, SBCLK high to SXAL low in the TX cycle or
SALE low in the T1 cycle
0
25
0
25
218
Hold time, SADH0–SADH7, SADL0–SADL7, SPH, and
SPL valid after SALE or SXAL low
5
5
223R Delay time, SBCLK low in T4 cycle to SRD high (see Note 27)
0
16
0
11
225R Delay time, SBCLK low in T4 cycle to SDBEN high
16
11
Delay time, SADH0–SADH7, SADL0–SADL7, SPH, and
226 _{SPL in the high-impedance state to SRD low}
0
0
227R Delay time, SBCLK low in T2 cycle to SRD low
0
15
0
15
229
Hold time, SADH0–SADH7, SADL0–SADL7, SPH, and
SPL in the high-impedance state after SBCLK low in T1 cycle
0
0
231 Pulse duration, SRD low
Setup time, SADH0–SADH7, SADL0–SADL7, SPH, and
233 _{SPL valid before SALE, SXAL no longer high}
2tc(SCK)–25
10
2tc(SCK)–25
10
237R Delay time, SBCLK high in the T2 cyle to SDBEN low
16
11
247 Setup time, data valid before SRDY low if parameter 208a not met
0
0
NOTE 27: While the system-interface DMA controls are active (that is, SOWN is asserted), SCS is disabled.
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
58
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265