TI380C30A Datasheet, PDF (60/81 Pages) Texas Instruments – INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE

TI380C30A
INTEGRATED TOKEN-RING COMMPROCESSOR
AND PHYSICAL-LAYER INTERFACE
SPWS034 – MARCH 1998
80x8x-mode DMA write cycle (see Figure 25)
NO.
208a
Setup time, asynchronous signal SRDY before SBCLK no longer high to
assure recognition on that cycle
208b
Hold time, asynchronous signal SRDY after SBCLK low to assure
recognition on that cycle
212
Delay time, SBCLK low to SADH0–SADH7, SADL0–SADL7, SPH, and
SPL valid
216 Delay time, SBCLK high to SALE or SXAL high
216a Hold time, SALE or SXAL low after SWR high
217
Delay time, SBCLK high to SXAL low in the TX cycle or
SALE low in the T1 cycle
218 Hold time, address valid after SALE, SXAL low
219 Delay time, SBCLK low in T2 cycle to output data and parity valid
221
Hold time, SADH0–SADH7, SADL0–SADL7, SPH, and
SPL valid after SWR high
223W Delay time, SBCLK low to SWR high
225W Delay time, SBCLK high in T4 cycle to SDBEN high
225WH Hold time, SDBEN low after SWR, SUDS, and SLDS high
227W Delay time, SBCLK low in T2 cycle to SWR low
Setup time, SADH0–SADH7, SADL0–SADL7, SPH, and
233 _{SPL valid before SALE, SXAL no longer high}
237W Delay time, SBCLK high in T1 cycle to SDBEN low
25-MHZ
OPERATION
MIN MAX
10
10
20
20
0
0
25
5
29
tc(SCK)–12
0
16
16
tc(SCK)/2–7
0
20
10
16
33-MHZ
OPERATION
MIN MAX
10
10
20
20
0
0
25
5
29
tc(SCK)–12
0
11
11
tc(SCK)/2–7
0
15
10
11
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
60
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265