TI380C30A Datasheet, PDF (13/81 Pages) Texas Instruments – INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE

TI380C30A
INTEGRATED TOKEN-RING COMMPROCESSOR
AND PHYSICAL-LAYER INTERFACE
SPWS034 – MARCH 1998
Terminal Functions (Continued)
TERMINAL
NAME
NO.
I/O/E†
DESCRIPTION
SOWN
System bus owned. SOWN indicates to external devices that TI380C30A has control of the system bus.
SOWN drives the enable signal of the bus-transceiver chips that drive the address and bus-control
96
O
signals.
H = TI380C30A does not have control of the system bus
L = TI380C30A has control of the system bus
SPH
99
I/O
System parity high. SPH is the optional odd-parity bit for each address or data byte transmitted over
SADH0–SADH7 (see Note 1).
SPL
92
I/O
System parity low. SPL is the optional odd-parity bit for each address or data byte transmitted over
SADL0–SADL7 (see Note 1).
Intel
mode
SRAS is used for system memory-address strobe (see Note 7). SRAS is used to latch the
SCS and SRSX – SRS2 register input signals. In a minimum-chip system, SRAS is tied
to the SALE output of the system bus. The latching capability can be defeated since the
internal latch for these inputs remains transparent as long as SRAS remains high. This
permits SRAS to be pulled high and the signals at SCS, SRSX – SRS2, and SBHE to be
applied independently of the SALE strobe from the system bus. During DMA, SRAS
remains an input.
SRAS/SAS
76
I/O
H = Transparent mode
L = Holds latched values of SCS, SRSX–SRS2, and SBHE
Falling edge = Latches SCS, SRSX – SRS2, and SBHE
Motorola
mode
SAS is used for sytem-memory address strobe (see Note 7). SAS is an active-low
address strobe that is an input during DIO (although ignored as an address strobe) and
an output during DMA.
H = Address is not valid
L = Address is valid and a transfer operation is in progress
SRD/SUDS
Intel
mode
98
I/O
SRD is used for system-read strobe (see Note 7). SRD is the active-low strobe indicating
that a read cycle is performed on the system bus. SRD is an input during DIO and an
output during DMA.
H = Read cycle is not occurring
L = If DMA, host provides data to system bus. If DIO, SIF provides data to system bus
Motorola
mode
SUDS is used for upper-data strobe (see Note 7). SUDS is the active-low upper-data
strobe. SUDS is an input during DIO and an output during DMA.
H = Not valid data on SADH0–SADH7 lines
L = Valid data on SADH0–SADH7 lines
Intel
mode
SRDY is used for system bus ready (see Note 7). SRDY indicates to the bus master that
a data transfer is complete. SRDY is asynchronous, but during DMA and pseudo-DMA
cycles, it is internally synchronized to SBCLK. During DMA cycles, SRDY must be
asserted before the falling edge of SBCLK in state T2 in order to prevent a wait state.
SRDY is an output when the TI380C30A is selected for DIO; otherwise, it is an input.
SRDY/SDTACK 97
H = System bus is not ready
L = Data transfer is complete; system bus is ready
I/O
SDTACK is used for system data-transfer acknowledge (see Note 7). The purpose of
SDTACK is to indicate to the bus master that a data transfer is complete. SDTACK is
Motorola
mode
internally synchronized to SBCLK. During DMA cycles, SDTACK must be asserted before
the falling edge of SBCLK in state T2 in order to prevent a wait state. SDTACK is an output
when the TI380C30A is selected for DIO; otherwise, it is an input.
H = System bus is not ready
L = Data transfer is complete; system bus is ready
† _{I = input, O = output, E = provides external-component connection to the internal circuitry for tuning}
NOTES: 1. Terminal has an internal pullup device to maintain a high-voltage level when left unconnected (no etch).123456
7. Terminal should be tied to VDD with a 4.7-kΩ pullup resistor.
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