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TI380C30A Datasheet, PDF (14/81 Pages) Texas Instruments – INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE
TI380C30A
INTEGRATED TOKEN-RING COMMPROCESSOR
AND PHYSICAL-LAYER INTERFACE
SPWS034 – MARCH 1998
Terminal Functions (Continued)
TERMINAL
NAME
NO.
I/O/E†
DESCRIPTION
SRESET
System reset. SRESET is activated to place the TI380C30A into a known initial state. Hardware reset
puts most of the TI380C30A outputs into the high-impedance state and places all blocks into the reset
state. The Intel-mode DMA bus-width selection (S8) is latched on the rising edge of SRESET.
62
I
H = No system reset
L = System reset
Rising edge = Latch bus width for DMA operations (for Intel-mode applications)
Intel
mode
SRSX and SRS0–SRS2 are used for system-register select. These inputs select the
word or byte to be transferred during a system DIO access. The MSB is SRSX and the
LSB is SRS2 (see Note 1).
MSB
LSB
Register selected = SRSX SRS0 SRS1 SRS2/SBERR
SRSX
65
SRS0
64
SRS1
63
SRS2/SBERR
70
SRSX, SRS0, and SRS1 are used for system-register select. These inputs select the
word or byte to be transferred during a system DIO access. The most significant bit is
I
SRSX and the least significant bit is SRS1 (see Note 1).
Motorola
mode
MSB
LSB
Register selected = SRSX SRS0 SRS1
SBERR is used for bus error. SBERR corresponds to the bus-error signal of the 68xxx
microprocessor. It is internally synchronized to SBCLK. SBERR is driven low during a
DMA cycle to indicate to the TI380C30A that the cycle must be terminated (see
section 3.4.5.3 of the TMS380 Second-Generation Token-Ring User’s Guide, literature
number SPWU005, for more information).
SWR/SLDS
Intel
mode
77
I/O
SWR is used for system-write strobe (see Note 7). SWR is an active-low write strobe
that is an input during DIO and an output during DMA.
H = Write cycle is not occurring
L = If DMA, data to be driven from SIF to host bus. If DIO, on the rising edge, the data
is latched and written to the selected register
Motorola
mode
SLDS is used for lower-data strobe (see Note 7). SLDS is an input during DIO and an
output during DMA.
H = Not valid data on SADL0–SADL7 lines
L = Valid data on SADL0–SADL7 lines
SXAL
System extended-address latch. SXAL provides the enable pulse used to externally latch the most
significant 16 bits of the 32-bit system address during DMA. SXAL is activated prior to the first cycle
79
O
of each block DMA transfer, and thereafter as necessary (whenever an increment of the DMA address
counter causes a carry-out of the lower 16 bits). Systems that implement parity on addresses can use
SXAL to externally latch the parity bits (available on SPL and SPH) for the DMA address extension.
SYNCIN
12
I
Reserved. SYNCIN must be left unconnected (see Note 1).
Speed switch. S4/16 specifies the token-ring data rate for the physical layer (see Note 1).
S4/16
155
I
H = 4-Mbit/s data rate
L = 16-Mbit/s data rate
† I = input, O = output, E = provides external-component connection to the internal circuitry for tuning
NOTES: 1. Terminal has an internal pullup device to maintain a high-voltage level when left unconnected (no etch).123456
7. Terminal should be tied to VDD with a 4.7-kΩ pullup resistor.
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