TI380C30A Datasheet, PDF (18/81 Pages) Texas Instruments – INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE

TI380C30A
INTEGRATED TOKEN-RING COMMPROCESSOR
AND PHYSICAL-LAYER INTERFACE
SPWS034 – MARCH 1998
system interface (SIF) (continued)
The system-interface hardware also includes features to enhance the integrity of the TI380C30A operation and
the data. These features include:
D Always internally maintain odd-byte parity regardless of parity being disabled
D Monitor for the presence of a clock failure
D Provide switchable SIF speeds at 2 MHz to 33 MHz
On every cycle, the system interface compares all the system clocks to a reference clock. If any of the clocks
becomes invalid, the TI380C30A enters the slow-clock mode, which prevents latch-up of the TI380C30A. If the
SBCLK is invalid, any DMA cycle is terminated immediately; otherwise, the DMA cycle is completed and the
TI380C30A is placed in slow-clock mode.
When the TI380C30A enters the slow-clock mode, the clock that failed is replaced by a slow free-running clock,
and the device is placed into a low-power reset state. When the failed clock(s) return to valid operation, the
TI380C30A must be reinitialized.
For DMA with a 16-MHz clock, a continuous transfer rate of 64 MBps [8 megabytes per second (MBps)] can
be obtained. For DMA with a 25-MHz clock, a continuous transfer rate of 96 Mbit/s (12 MBps) can be obtained.
For DMA with a 33-MHz clock, a continuous transfer rate of 128 Mbit/s (16 MBps) can be obtained. For 8-bit
and 16-bit pseudo-DMA, the data rates in Table 2 can be obtained.
Table 2. Pseudo-DMA Data Rates
LOCAL
BUS SPEED
4 MHz
6 MHz
8-BIT
PDMA
48 Mbit/s
72 Mbit/s
16-BIT
PDMA
64 Mbit/s
96 Mbit/s
Since the main purpose of DIO is for downloading and initialization, the DIO transfer rate is not a significant
issue.
memory interface (MIF)
The MIF performs memory management to allow the TI380C30A to address 2 Mbytes in local memory.
Hardware in the MIF allows the TI380C30A to be connected directly to DRAMs without additional circuitry. This
glueless-DRAM connection includes the DRAM-refresh controller. The MIF also handles all internal bus
arbitration between these blocks. When required, the MIF arbitrates for the external bus.
The MIF is responsible for the memory mapping of the CPU of a task. The memory maps of DRAMs, EPROMs,
burned-in addresses (BIAs), and external devices are addressed appropriately when required by the system
interface, the protocol handler, or for a DMA transfer. The memory interface is capable of a 64-Mbit/s continuous
transfer rate when using a 4-MHz local bus (64-MHz device crystal) and a 96-Mbit/s continuous transfer rate
when using a 6-MHz local bus.
protocol handler (PH)
The PH performs the hardware-based real-time protocol functions for a token-ring LAN. Network type is
determined by TEST0–TEST2. The token-ring network speed is determined by software and can be either
16 Mbit/s or 4 Mbit/s. These speeds are fixed by the software, not by the hardware.
The PH converts the parallel-transmit data to serial-network data of the appropriate coding and converts the
received serial data to parallel data. The PH data-management state machines direct the
transmission/reception of data to/from local memory through the MIF. The PH buffer-management state
machines automatically oversee this process, directly sending/receiving linked lists of frames without CPU
intervention.
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