TI380C30A Datasheet, PDF (33/81 Pages) Texas Instruments – INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE

TI380C30A
INTEGRATED TOKEN-RING COMMPROCESSOR
AND PHYSICAL-LAYER INTERFACE
SPWS034 – MARCH 1998
electrical characteristics over recommended ranges of supply voltage and operating case
temperature (unless otherwise noted) (continued)
crystal-oscillator characteristics
PARAMETER
VSB(XT1)
IOH(XT2)
IOL(XT2)
Input self-bias voltage
Output high-level current
Output low-level current
TEST CONDITIONS
V(XT2) = VSB(XT1), V(XT1) = VSB(XT1) + 0.5 V
V(XT2) = VSB(XT1), V(XT1) = VSB(XT1) – 0.5 V
MIN MAX UNIT
1.8
4V
–2.5 –6.5 mA
0.4 1.3 mA
timing parameters
The timing parameters for the signals of TI380C30A are shown in the following tables and are illustrated in the
accompanying figures. The purpose of these figures and tables is to quantify the timing relationships among
the various signals. The parameters are numbered for convenience.
static signals
Table 6 lists signals that are not allowed to change dynamically and therefore have no timing associated with
them. They should be strapped high, low, or left unconnected as required.
Table 6. Static Signals and Functions
SIGNAL
FUNCTION
SI/M
Host-processor select (Intel/Motorola)
CLKDIV Clock divider select
BTSTRP Default-bootstrap mode (RAM/ROM)
PRTYEN Default-parity select (enabled/disabled)
TEST0 Test pin indicates network type
TEST1 NC
TEST2 Test pin indicates network type
TEST3
Test pin for TI manufacturing test†
TEST4
Test pin for TI manufacturing test†
TEST5
Test pin for TI manufacturing test†
† _{For unit-in-place test}
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
33