TI380C30A Datasheet, PDF (57/81 Pages) Texas Instruments – INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE

TI380C30A
INTEGRATED TOKEN-RING COMMPROCESSOR
AND PHYSICAL-LAYER INTERFACE
SPWS034 – MARCH 1998
80x8x-mode bus-arbitration timing
80x8x-mode bus arbitration – SIF takes control (see Figure 23)
25-MHZ
33-MHZ
NO.
OPERATION
OPERATION
MIN MAX
MIN MAX
208a
Setup time, asynchronous signal SBBSY and
SHLDA before SBCLK no longer high to assure recognition on that cycle
10
10
Hold time, asynchronous signal SBBSY and
208b _{SHLDA after SBCLK low to assure recognition on that cycle}
10
10
212
Delay time, SBCLK low to SADH0–SADH7, SADL0–SADL7, SPH, and
SPL valid
20
20
224a Delay time, SBCLK low in cycle I2 to SOWN low
0
20
0
15
224c Delay time, SBCLK low in cycle I2 to SDDIR low in DMA read
28
23
230 Delay time, SBCLK high to SHRQ high
20
15
Delay time, SBCLK high in TX cycle to SRD and
241 _{SWR high, bus acquisition}
25
25
241a
Hold time, SRD and SWR in the high-impedance state after SOWN low,
bus acquisition
tc(SCK)–15
tc(SCK)–15
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
User Master
Bus Exchange
SIF Master
SIF
Inputs
SBCLK
SBBSY
SHLDA
208a
230
208b
SIF
Outputs
SHRQ
SRD
SWR
SBHE
SADH0–
SADH7
SADL0–
SADL7
SPH
SPL
SDDIR
SOWN^†
241
241a
212
224c
224a
212
Address Valid
Write
Read
† _{While the system interface DMA controls are active (that is, SOWN is asserted), the SCS input is disabled.}
Figure 23. 80x8x-Mode Bus Arbitration – SIF Takes Control
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