TI380C30A Datasheet, PDF (75/81 Pages) Texas Instruments – INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE

SBCLK
SAS
SUDS
SLDS
SRNW
SXAL
SALE
SADL0–SADH7
SADH0–SADL7
SPL
SPH
SDTACK‡§
TI380C30A
INTEGRATED TOKEN-RING COMMPROCESSOR
AND PHYSICAL-LAYER INTERFACE
SPWS034 – MARCH 1998
TWAIT
V
T4
TX
T1
T2
T3
T4
T1
†
222
211
223W
233a
209
216
Low
218
217
216
211
a
217
218
216a
212
212
233
233
219
221
Address
Output Data
Extended Address
208b
SDDIR
Low
237W
208b
225W
225WH
SDBEN
† _{In cycle-steal mode, state TX is present on every system bus transfer. In burst mode, state TX is present on the first bus transfer and whenever}
the increment of the DMA address register carries beyond the least significant 16 bits.
‡ _{On a read cycle, the read strobe remains active until the internal sample of incoming data is completed. Input data can be removed}
when either the read strobe or SDBEN becomes inactive.
§ _{All VSS terminals should be routed to minimize inductance to system ground.}
Figure 33. 68xxx-Mode DMA Write Cycle
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