TI380C30A Datasheet, PDF (21/81 Pages) Texas Instruments – INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE

TI380C30A
INTEGRATED TOKEN-RING COMMPROCESSOR
AND PHYSICAL-LAYER INTERFACE
SPWS034 – MARCH 1998
VDD
LOAD
LOAD
RCV+
RCV–
DATA
External Equalizer
DATA
WRAP
EQ+ _R1
R2
EQ–
From DRVR+/DRVR–
IEQB
C1
IEQB
VSS
Figure 3. Line Receiver/Equalizer
receiver-clock recovery
The clock and data recovery in the TI380C30A is performed by an advanced, digitally controlled PLL. In contrast
to the TMS38054, the PLL of the TI380C30A is digitally controlled and the loop parameters are set by internally
programmed digital constants. This results in precise control of loop parameters and requires no external
loop-filter components.
The TI380C30A implements an intelligent algorithm to determine the optimum phase position for data sampling
and extracted-clock synthesis. The resulting action of the TI380C30A can be modeled as two cascaded PLLs
as shown in Figure 4.
RCV Data
PLL1
PLL2
f3dB ≅ _{680 kHz}
(see Note A)
f3dB ≅ _{162 kHz}
(see Note A)
NOTE A: f3dB = 3-dB bandwidth of PLL
Figure 4. Dual-PLL Arrangement
RCLK
RCVR
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
21