TI380C30A Datasheet, PDF (44/81 Pages) Texas Instruments – INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE

TI380C30A
INTEGRATED TOKEN-RING COMMPROCESSOR
AND PHYSICAL-LAYER INTERFACE
SPWS034 – MARCH 1998
memory-bus timing (continued)
t_M is the cycle time of one-eighth of a local-memory cycle (31.25 ns minimum for a 4-MHz local bus or 20.83 ns
minimum for a 6-MHz local bus).
memory-bus read cycle (see Figure 13)
NO.
MIN
MAX UNIT
32 Access time, address/enable valid on MAX0, MAX2, and MROMEN to valid data/parity
33
Access time, address valid on MAXPH, MAXPL, MADH0–MADH7,
and MADL0–MADL7 to valid data/parity
6tM–23 ns
6tM–23
ns
35 Access time, MRAS low to valid data/parity
36 Hold time, valid data/parity after MRAS no longer low
4.5tM–21.5 ns
0
ns
37
Hold time, address in the high-impedance state on MAXPH, MAXPL, MADH0–MADH7
and MADL0–MADL7 after MRAS high (see Note 22)
2tM–10.5
ns
38 Access time, MCAS low to valid data/parity
39 Hold time, valid data/parity after MCAS no longer low
3tM–23 ns
0
ns
40
Hold time, address in the high-impedance state on MAXPH, MAXPL, MADH0–MADH7,
and MADL0–MADL7 after MCAS high (see Note 22)
2tM–13
ns
41 Delay time, MCAS no longer high to MOE low
42
Setup time, address/status in the high-impedance state on MAXPH, MAXPL, MADL0–MADL7,
and MADH0–MADH7 before MOE no longer high
tM+13 ns
0
ns
43 Access time, MOE low to valid data/parity
44 Pulse duration, MOE low
45 Delay time, MCAS low to MOE no longer low
46 Hold time, valid data/parity in after MOE no longer low
2tM–9
3tM–9
0
2tM–20 ns
ns
ns
ns
47
Hold time, address in the high-impedance state on MAXPH, MAXPL, MADH0–MADH7,
and MADL0–MADL7 after MOE high (see Note 22)
2tM–15
ns
48
Setup time, address/status in the high-impedance state on MAXPH, MAXPL, MADL0–MADL7,
and MADH0–MADH7, before MBEN no longer high
0
ns
48a
Setup time, address/status in the high-impedance state on MAXPH, MAXPL, MADL0–MADL7,
and MADH0–MADH7 and before MBIAEN no longer high
0
ns
49 Access time, MBEN low to valid data/parity
49a Access time, MBIAEN low to valid data/parity
50 Pulse duration, MBEN low
50a Pulse duration, MBIAEN low
51 Hold time, valid data/parity after MBEN no longer low
2tM–9
2tM–9
0
2tM–25 ns
2tM–25 ns
ns
ns
ns
51a Hold time, valid data/parity after MBIAEN no longer low
0
ns
52
Hold time, address in the high-impedance state on MAXPH, MAXPL, MADH0–MADH7,
and MADL0–MADL7 after MBEN high (see Note 22)
2tM–15
ns
52a
Hold time, address in the high-impedance state on MAXPH, MAXPL, MADH0–MADH7,
and MADL0–MADL7 after MBIAEN high
2tM–15
ns
53 Hold time, MDDIR high after MBEN high, read follows write cycle
1.5tM–12
ns
54 Setup time, MDDIR low before MBEN no longer high
3tM–5
ns
55 Hold time, MDDIR low after MBEN high, write follows read cycle
3tM–12
ns
NOTE 22: The data/parity that exists on the address lines most likely will reach the high-impedance state some time later than the rising edge
of MRAS, MCAS, MOE, or MBEN (between MIN and MAX of timing parameter 36) and will be a function of the memory being read.
The MIN time given represents the time from the rising edge of MRAS, MCAS, MOE, or MBEN to the beginning of the next address,
and does not represent the actual high-impedance period on the address bus.
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