TI380C30A Datasheet, PDF (7/81 Pages) Texas Instruments – INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE

TI380C30A
INTEGRATED TOKEN-RING COMMPROCESSOR
AND PHYSICAL-LAYER INTERFACE
SPWS034 – MARCH 1998
Terminal Functions
TERMINAL
NAME
NO.
I/O/E†
DESCRIPTION
ATEST
128
E
Analog test. ATEST must be left unconnected.
BTSTRP
Bootstrap. The value on BTSTRP is loaded into the BOOT bit of the SIFACL register at reset (that is,
when SRESET is asserted or the ARESET bit in the SIFACL register is set) to form a default value.
BTSTRP indicates whether chapters 0 and 31 of the memory map are RAM or ROM. If these chapters
60
I
are RAM, the TI380C30A is denied access to the local-memory bus until the CPHALT bit in the
SIFACL register is cleared.
H = Chapters 0 and 31 of local memory are RAM based (see Note 1).
L = Chapters 0 and 31 of local memory are ROM based.
CLKDIV
Clock divider select (see Note 2)
56
I
H = 64-MHz OSCIN for 4-MHz local bus
L = 32-MHz OSCIN for 4-MHz local bus or 48-MHz OSCIN for 6-MHz local bus
DRVR+
DRVR–
169
O
168
O
Differential-driver data outputs (reserved)
EQ+
EQ–
152
151
E
E
Equalization/gain points. Connections to allow frequency tuning of equalization circuit.
EXTINT0
EXTINT1
EXTINT2
EXTINT3
54
53
52
I/O
Reserved. EXTINT0–EXTINT3 must be pulled high (see Note 3).
51
FRAQ
Frequency-acquisition control
122
To be
resolved
H = Clock recovery PLL is initialized
L = Normal operation
IREF
126
E
Internal reference. IREF allows the internal bias current of analog circuitry to be set by way of an
external resistor.
MACS
3
I
Reserved. MACS must be tied low (see Note 4).
MADH0
MADH1
MADH2
MADH3
MADH4
MADH5
MADH6
MADH7
34
Local-memory address, data, and status bus – high byte. For the first quarter of the local-memory
33
cycle, these bus lines carry address bits AX4 and A0–A6; for the second quarter, they carry status
32
bits; and for the third and fourth quarters, they carry data bits D0–D7. The most significant bit is
31
28
I/O
MADH0 and the least significant bit is MADH7.
27
Memory Cycle
26
1Q
2Q
3Q
4Q
25
Signal AX4, A0–A6 Status D0–D7 D0–D7
MADL0
MADL1
MADL2
MADL3
MADL4
MADL5
MADL6
MADL7
50
Local-memory address, data, and status bus — low byte. For the first quarter of the local-memory
49
cycle, these bus lines carry address bits A7–A14; for the second quarter, they carry address bits AX4
48
and A0–A6; and for the third and fourth quarters, they carry data bits D8–D15. The most significant
44
43
I/O
bit is MADL0 and the least significant bit is MADL7.
42
Memory Cycle
41
1Q
2Q
3Q
4Q
40
Signal A7–A14 AX4, A0–A6 D8–D15 D8–D15
MAL
Memory-address latch. MAL is a strobe signal for sampling the address at the start of the memory
cycle; it is used by SRAMs and EPROMs. The full 20-bit word address is valid on MAX0, MAXPH,
MAX2, MAXPL, MADH0–MADH7, and MADL0–MADL7. Three 8-bit transparent latches can be used
2
O
to retain a 20-bit static address throughout the cycle.
Rising edge = No signal latching
Falling edge = Allows the above address signals to be latched
† _{I = input, O = output, E = provides external-component connection to the internal circuitry for tuning}
NOTES: 1. Terminal has an internal pullup device to maintain a high-voltage level when left unconnected (no etch).
2. The TMS380SRA is supported only with the 4-MHz local bus in either CLKDIV state.
3. Each terminal must be tied individually to VDD with a 1-kΩ pullup resistor.
4. Terminal should be connected to ground.
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